.cpu arm9 .fpu softvfp .file "sdcore2.c" .section .rodata.destagger,"a",%progbits .type destagger, %object .size destagger, 256 destagger: .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 0 .byte 1 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .byte 2 .byte 3 .section .rodata.crc16tbl,"a",%progbits .align 1 .type crc16tbl, %object .size crc16tbl, 512 crc16tbl: .short 0 .short 4129 .short 8258 .short 12387 .short 16516 .short 20645 .short 24774 .short 28903 .short -32504 .short -28375 .short -24246 .short -20117 .short -15988 .short -11859 .short -7730 .short -3601 .short 4657 .short 528 .short 12915 .short 8786 .short 21173 .short 17044 .short 29431 .short 25302 .short -27847 .short -31976 .short -19589 .short -23718 .short -11331 .short -15460 .short -3073 .short -7202 .short 9314 .short 13379 .short 1056 .short 5121 .short 25830 .short 29895 .short 17572 .short 21637 .short -23190 .short -19125 .short -31448 .short -27383 .short -6674 .short -2609 .short -14932 .short -10867 .short 13907 .short 9842 .short 5649 .short 1584 .short 30423 .short 26358 .short 22165 .short 18100 .short -18597 .short -22662 .short -26855 .short -30920 .short -2081 .short -6146 .short -10339 .short -14404 .short 18628 .short 22757 .short 26758 .short 30887 .short 2112 .short 6241 .short 10242 .short 14371 .short -13876 .short -9747 .short -5746 .short -1617 .short -30392 .short -26263 .short -22262 .short -18133 .short 23285 .short 19156 .short 31415 .short 27286 .short 6769 .short 2640 .short 14899 .short 10770 .short -9219 .short -13348 .short -1089 .short -5218 .short -25735 .short -29864 .short -17605 .short -21734 .short 27814 .short 31879 .short 19684 .short 23749 .short 11298 .short 15363 .short 3168 .short 7233 .short -4690 .short -625 .short -12820 .short -8755 .short -21206 .short -17141 .short -29336 .short -25271 .short 32407 .short 28342 .short 24277 .short 20212 .short 15891 .short 11826 .short 7761 .short 3696 .short -97 .short -4162 .short -8227 .short -12292 .short -16613 .short -20678 .short -24743 .short -28808 .short -28280 .short -32343 .short -20022 .short -24085 .short -12020 .short -16083 .short -3762 .short -7825 .short 4224 .short 161 .short 12482 .short 8419 .short 20484 .short 16421 .short 28742 .short 24679 .short -31815 .short -27752 .short -23557 .short -19494 .short -15555 .short -11492 .short -7297 .short -3234 .short 689 .short 4752 .short 8947 .short 13010 .short 16949 .short 21012 .short 25207 .short 29270 .short -18966 .short -23093 .short -27224 .short -31351 .short -2706 .short -6833 .short -10964 .short -15091 .short 13538 .short 9411 .short 5280 .short 1153 .short 29798 .short 25671 .short 21540 .short 17413 .short -22565 .short -18438 .short -30823 .short -26696 .short -6305 .short -2178 .short -14563 .short -10436 .short 9939 .short 14066 .short 1681 .short 5808 .short 26199 .short 30326 .short 17941 .short 22068 .short -9908 .short -13971 .short -1778 .short -5841 .short -26168 .short -30231 .short -18038 .short -22101 .short 22596 .short 18533 .short 30726 .short 26663 .short 6336 .short 2273 .short 14466 .short 10403 .short -13443 .short -9380 .short -5313 .short -1250 .short -29703 .short -25640 .short -21573 .short -17510 .short 19061 .short 23124 .short 27191 .short 31254 .short 2801 .short 6864 .short 10931 .short 14994 .short -722 .short -4849 .short -8852 .short -12979 .short -16982 .short -21109 .short -25112 .short -29239 .short 31782 .short 27655 .short 23652 .short 19525 .short 15522 .short 11395 .short 7392 .short 3265 .short -4321 .short -194 .short -12451 .short -8324 .short -20581 .short -16454 .short -28711 .short -24584 .short 28183 .short 32310 .short 20053 .short 24180 .short 11923 .short 16050 .short 3793 .short 7920 .section .text.sd_initcrc,"ax",%progbits .align 2 .type sd_initcrc, %function sd_initcrc: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 @ link register save eliminated. @ lr needed for prologue mov r1, r0 mov r2, r0 mov ip, #3 .L5: mov r3, #0 subs ip, ip, #1 strh r3, [r1, #144] @ movhi str r3, [r2, #152] add r1, r1, #2 add r2, r2, #4 bpl .L5 add r3, r3, #6 str r3, [r0, #140] bx lr .size sd_initcrc, .-sd_initcrc .section .text.sd_1bit_feedcrc,"ax",%progbits .align 2 .type sd_1bit_feedcrc, %function sd_1bit_feedcrc: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 @ link register save eliminated. ldrh r2, [r0, #144] ldr r3, .L10 mov r2, r2, asl #16 eor r1, r1, r2, lsr #24 mov r1, r1, asl #1 ldrh r3, [r1, r3] @ lr needed for prologue eor r3, r3, r2, lsr #8 strh r3, [r0, #144] @ movhi bx lr .L11: .align 2 .L10: .word crc16tbl .size sd_1bit_feedcrc, .-sd_1bit_feedcrc .section .text.sd_4bit_feedcrc,"ax",%progbits .align 2 .type sd_4bit_feedcrc, %function sd_4bit_feedcrc: @ Function supports interworking. @ args = 0, pretend = 0, frame = 8 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} ldr r3, .L18 ldr r2, [r0, #140] ldrb lr, [r3, r1] @ zero_extendqisi2 mov r1, r1, lsr #1 mov r7, r0 ldrb r0, [r3, r1] @ zero_extendqisi2 mov r1, r1, lsr #1 and fp, r2, #7 ldrb ip, [r3, r1, lsr #1] @ zero_extendqisi2 sub r4, r2, #2 ldr sl, [r7, #156] ldr r2, [r7, #152] ldr r9, [r7, #160] ldr r8, [r7, #164] ldrb r3, [r3, r1] @ zero_extendqisi2 sub sp, sp, #12 cmp fp, #0 str r4, [sp, #4] orr r2, r2, lr, asl fp orr sl, sl, r0, asl fp orr r9, r9, r3, asl fp orr r8, r8, ip, asl fp bne .L13 ldrh lr, [r7, #144] ldrh r4, [r7, #146] ldrh r5, [r7, #148] ldrh r6, [r7, #150] mov lr, lr, asl #16 mov r4, r4, asl #16 mov r5, r5, asl #16 mov r6, r6, asl #16 eor r1, sl, r4, lsr #24 eor r0, r9, r5, lsr #24 eor r3, r8, r6, lsr #24 eor r2, r2, lr, lsr #24 ldr r8, .L18+4 mov r2, r2, asl #1 mov r1, r1, asl #1 mov r3, r3, asl #1 mov r0, r0, asl #1 ldrh ip, [r3, r8] ldrh r3, [r2, r8] ldrh r2, [r1, r8] ldrh r1, [r0, r8] eor r2, r2, r4, lsr #8 eor r3, r3, lr, lsr #8 eor r1, r1, r5, lsr #8 eor ip, ip, r6, lsr #8 strh r2, [r7, #146] @ movhi mov r8, fp strh r3, [r7, #144] @ movhi strh r1, [r7, #148] @ movhi strh ip, [r7, #150] @ movhi mov r9, fp mov sl, fp mov r2, fp .L13: ldr r3, [sp, #4] str r2, [r7, #152] str r3, [r7, #140] str sl, [r7, #156] str r9, [r7, #160] str r8, [r7, #164] add sp, sp, #12 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} bx lr .L19: .align 2 .L18: .word destagger .word crc16tbl .size sd_4bit_feedcrc, .-sd_4bit_feedcrc .section .rodata.restaggertbl.0,"a",%progbits .type restaggertbl.0, %object .size restaggertbl.0, 4 restaggertbl.0: .byte 0 .byte 1 .byte 16 .byte 17 .section .rodata.restaggertbl_lsl1.1,"a",%progbits .type restaggertbl_lsl1.1, %object .size restaggertbl_lsl1.1, 4 restaggertbl_lsl1.1: .byte 0 .byte 2 .byte 32 .byte 34 .section .rodata.restaggertbl_lsl2.2,"a",%progbits .type restaggertbl_lsl2.2, %object .size restaggertbl_lsl2.2, 4 restaggertbl_lsl2.2: .byte 0 .byte 4 .byte 64 .byte 68 .section .rodata.restaggertbl_lsl3.3,"a",%progbits .type restaggertbl_lsl3.3, %object .size restaggertbl_lsl3.3, 4 restaggertbl_lsl3.3: .byte 0 .byte 8 .byte -128 .byte -120 .section .text.sd_4bit_getcrc,"ax",%progbits .align 2 .type sd_4bit_getcrc, %function sd_4bit_getcrc: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, lr} ldr r3, .L21 ldrh ip, [r0, #144] ldrh lr, [r0, #146] ldrh r4, [r0, #148] mov r2, r0 ldrb r0, [r3, ip, lsr #14] @ zero_extendqisi2 ldr r3, .L21+4 ldrh r1, [r2, #150] ldrb r5, [r3, lr, lsr #14] @ zero_extendqisi2 ldr r3, .L21+8 orr r0, r0, r5 ldrb r6, [r3, r4, lsr #14] @ zero_extendqisi2 ldr r3, .L21+12 orr r0, r0, r6 ldrb r3, [r3, r1, lsr #14] @ zero_extendqisi2 mov ip, ip, asl #2 mov lr, lr, asl #2 mov r4, r4, asl #2 mov r1, r1, asl #2 orr r0, r0, r3 strh r1, [r2, #150] @ movhi strh ip, [r2, #144] @ movhi strh lr, [r2, #146] @ movhi strh r4, [r2, #148] @ movhi ldmfd sp!, {r4, r5, r6, lr} bx lr .L22: .align 2 .L21: .word restaggertbl.0 .word restaggertbl_lsl1.1 .word restaggertbl_lsl2.2 .word restaggertbl_lsl3.3 .size sd_4bit_getcrc, .-sd_4bit_getcrc .section .text.sd_1bit_getcrc,"ax",%progbits .align 2 .type sd_1bit_getcrc, %function sd_1bit_getcrc: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 @ link register save eliminated. mov r3, r0 ldrh r0, [r0, #144] @ lr needed for prologue mov r2, r0, asl #8 mov r0, r0, lsr #8 strh r2, [r3, #144] @ movhi bx lr .size sd_1bit_getcrc, .-sd_1bit_getcrc .section .text.sdsize,"ax",%progbits .align 2 .type sdsize, %function sdsize: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, lr} mov lr, r0 ldr r0, [r0, #188] cmp r0, #0 bne .L24 ldr r3, [lr, #76] ldr r1, [lr, #108] ldr ip, [lr, #112] tst r3, #192 and r3, r1, #192 orrne r1, ip, r1, asl #8 mov r4, r3, lsr #6 movne r3, r1, asl #10 addne r3, r3, #1024 bne .L28 ldr r2, [lr, #116] add r0, lr, #96 ldmia r0, {r0, r1, r3} @ phole ldm and r2, r2, #128 orr r3, r4, r3, asl #2 and ip, ip, #3 and r1, r1, #3 mov r2, r2, lsr #7 orr r1, r3, r1, asl #10 orr r2, r2, ip, asl #1 and r0, r0, #15 sub r0, r0, #9 add r1, r1, #1 add r2, r2, #2 mov r3, #1 mov r3, r3, asl r0 mov r1, r1, asl r2 mul r3, r1, r3 .L28: str r3, [lr, #188] ldr r0, [lr, #188] .L24: ldmfd sp!, {r4, lr} bx lr .size sdsize, .-sdsize .section .text.tend_ssp,"ax",%progbits .align 2 .type tend_ssp, %function tend_ssp: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, lr} ldr lr, [r0, #0] mov r4, r0 ldrb r3, [lr, #2] @ zero_extendqisi2 sub sp, sp, #4 tst r3, #8 mov ip, r1 mov r0, r2 and r5, r3, #255 beq .L30 ldr r3, [r4, #4] ands r2, r3, #4 beq .L31 ldrb r3, [lr, #0] @ zero_extendqisi2 cmp r1, #0 and r1, r3, #255 ldrne r3, [ip, #0] strne r1, [r3], #4 strne r3, [ip, #0] movne r3, #0 strne r3, [r4, #168] b .L30 .L31: tst r3, #8 beq .L30 ldr r3, [r1, #0] ldr r3, [r3, #0] strb r3, [lr, #0] ldr r3, [r1, #0] str r2, [r4, #168] add r3, r3, #4 str r3, [r1, #0] .L30: tst r5, #16 beq .L37 ldr r3, [r4, #4] ands r2, r3, #1 beq .L38 ldr r3, [r4, #0] cmp r0, #0 ldrb r3, [r3, #1] @ zero_extendqisi2 and r1, r3, #255 beq .L37 ldr r3, [r0, #0] mov r2, #0 strb r1, [r3, #0] ldr r3, [r0, #0] str r2, [r4, #168] add r3, r3, #1 str r3, [r0, #0] b .L37 .L38: tst r3, #2 beq .L37 cmp r0, #0 str r2, [r4, #168] beq .L44 ldr r3, [r0, #0] ldr r2, [r4, #0] ldrb r1, [r3], #1 @ zero_extendqisi2 str r3, [r0, #0] strb r1, [r2, #1] ldr r3, [r4, #4] tst r3, #16 bne .L37 tst r3, #32 beq .L46 mov r0, r4 bl sd_4bit_feedcrc b .L37 .L46: mov r0, r4 bl sd_1bit_feedcrc b .L37 .L44: tst r3, #16 bne .L50 tst r3, #32 beq .L51 mov r0, r4 bl sd_4bit_getcrc b .L50 .L51: mov r0, r4 bl sd_1bit_getcrc .L50: ldr r3, [r4, #0] strb r0, [r3, #1] .L37: mov r0, r5 add sp, sp, #4 ldmfd sp!, {r4, r5, lr} bx lr .size tend_ssp, .-tend_ssp .section .text.error,"ax",%progbits .align 2 .type error, %function error: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, lr} ldr r3, [r0, #0] and r1, r1, #63 cmp r1, r3 bne .L71 mov ip, #0 mov lr, r0 mov r5, ip .L64: ldrb r1, [lr, #0] @ zero_extendqisi2 mov r4, #0 .L63: add r3, r4, #1 mov ip, ip, asl #1 and r4, r3, #255 eor r3, r1, ip tst r3, #128 mov r2, r1, asl #1 eorne ip, ip, #9 cmp r4, #7 and r1, r2, #255 bls .L63 add r5, r5, #1 cmp r5, #5 and ip, ip, #127 add lr, lr, #4 bcc .L64 mov r3, ip, asl #1 ldr r2, [r0, #20] orr r3, r3, #1 cmp r3, r2 beq .L66 .L71: mov r0, #1 b .L54 .L66: ldmib r0, {r2, r3} @ phole ldm ldr r1, [r0, #12] mov r3, r3, asl #16 orr r3, r3, r2, asl #24 ldr r2, [r0, #16] orr r3, r3, r1, asl #8 ldr r0, .L72 orr r3, r3, r2 and r0, r3, r0 .L54: ldmfd sp!, {r4, r5, lr} bx lr .L73: .align 2 .L72: .word -34013176 .size error, .-error .section .text.sdcmd2,"ax",%progbits .align 2 .type sdcmd2, %function sdcmd2: @ Function supports interworking. @ args = 4, pretend = 0, frame = 80 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} mov r4, r0 ldr r0, [r0, #176] sub sp, sp, #84 cmp r0, #2 movne fp, #0 moveq fp, #1 mov r1, r1, asl #16 mov r6, r2 cmp fp, #0 mov r2, #0 mov sl, r1, lsr #24 mov r9, r1, lsr #16 add r7, sp, #8 str r2, [sp, #4] bne .L76 cmp r0, #3 bne .L75 .L76: mov r2, #1 str r2, [sp, #4] .L75: cmp r3, #0 mov r0, r4 movne r5, r3 moveq r5, r7 bl activate cmp r0, #0 bne .L213 ldr r3, [r4, #4] mov r1, r6, lsr #24 ands r8, r3, #256 mov ip, r6, lsr #16 mov r2, r6, lsr #8 bne .L79 mov r3, r1, asl #16 orr r0, r3, r9, asl #24 ldr r1, [r4, #0] and r3, ip, #255 orr r0, r0, r3, asl #8 mvn r3, #64 cmp fp, #0 strb r3, [r1, #0] and r2, r2, #255 ldrne r3, [r4, #0] orr r0, r0, r2 strne r0, [r3, #8] bne .L81 ldr r3, [sp, #4] ldr r2, [r4, #0] cmp r3, #0 mov r1, r0, lsr #16 strneh r1, [r2, #8] @ movhi strneh r0, [r2, #8] @ movhi bne .L81 mov r3, r0, lsr #24 strb r3, [r2, #8] ldr r3, [r4, #0] mov r2, r0, lsr #8 strb r1, [r3, #8] ldr r3, [r4, #0] strb r2, [r3, #8] ldr r3, [r4, #0] strb r0, [r3, #8] .L81: ldr r3, [r4, #0] strb r6, [r3, #8] b .L84 .L79: str ip, [r7, #8] str r6, [r7, #16] str r1, [r7, #4] str r2, [r7, #12] str r9, [r7, #0] mov ip, r7 mov r6, r0 .L93: ldrb r1, [ip, #0] @ zero_extendqisi2 mov lr, #0 .L92: add r3, lr, #1 mov r0, r0, asl #1 and lr, r3, #255 eor r3, r1, r0 tst r3, #128 mov r2, r1, asl #1 eorne r0, r0, #9 cmp lr, #7 and r1, r2, #255 bls .L92 add r6, r6, #1 cmp r6, #5 and r0, r0, #127 add ip, ip, #4 bcc .L93 mov r3, r0, asl #1 orr r3, r3, #1 str r3, [r7, #20] mov r6, #0 .L107: ldr r2, [r4, #168] ldr r3, .L217 ldr r0, [r7], #4 cmp r2, r3 bhi .L84 add r3, r2, #1 str r3, [r4, #168] mov lr, #7 .L106: and r2, r0, #128 mov r2, r2, lsr #3 ldr r3, [r4, #0] orr r1, r2, #143 strb r1, [r3, #0] ldr r3, [r4, #0] orr r1, r2, #175 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 strb r1, [r3, #0] ldr r3, [r4, #0] subs lr, lr, #1 ldrb r2, [r3, #0] @ zero_extendqisi2 mov r0, r0, asl #1 ldrb r3, [r3, #0] @ zero_extendqisi2 bpl .L106 add r6, r6, #1 cmp r6, #5 bls .L107 .L84: cmp sl, #1 beq .L109 cmp sl, #7 beq .L112 cmp sl, #3 movne ip, #6 moveq ip, #17 .L215: ldr r2, [r4, #168] ldr r3, .L217 ldr r1, .L217+4 cmp r2, r3 add r1, r2, r1 add r2, r2, #1 bhi .L109 str r2, [r4, #168] ldr r2, [r4, #0] mvn r3, #32 cmp r9, #584 streq r1, [r4, #168] strb r3, [r2, #0] cmp r8, #0 ldrne r3, [r4, #0] ldr r2, [r4, #0] ldrneb r3, [r3, #0] @ zero_extendqisi2 ldrb r3, [r2, #0] @ zero_extendqisi2 mov r0, #0 tst r3, #16 beq .L117 mvn r3, #0 cmp r8, #0 strb r3, [r2, #0] ldrne r3, [r4, #0] ldrneb r3, [r3, #0] @ zero_extendqisi2 b .L215 .L117: ldr r2, [sp, #4] str r0, [r4, #168] bics r2, r2, fp moveq lr, #4 movne lr, #5 cmp r8, #0 beq .L216 mov r6, r0 cmp r0, ip .L210: bcs .L138 mov r0, #0 mov lr, #7 .L136: ldr r2, [r4, #0] mvn r3, #32 strb r3, [r2, #0] ldr r3, [r4, #0] ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r1, [r3, #0] @ zero_extendqisi2 mvn r2, #0 strb r2, [r3, #0] ldr r3, [r4, #0] and r1, r1, #16 mov r1, r1, lsr #4 adds lr, lr, r2 orr r0, r1, r0, asl #1 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r3, [r3, #0] @ zero_extendqisi2 bpl .L136 add r6, r6, #1 cmp r6, ip str r0, [r5], #4 b .L210 .L216: cmp ip, #0 beq .L138 cmp ip, #3 movls r3, #0 andhi r3, fp, #1 cmp r3, #0 beq .L141 ldr r3, [r4, #0] sub ip, ip, #4 ldr r1, [r3, #8] mov r3, r1, lsr #24 mov r2, r1, lsr #16 str r3, [r5], #4 and r2, r2, #255 mov r3, r1, lsr #8 str r2, [r5], #4 and r3, r3, #255 str r3, [r5], #4 and r3, r1, #255 str r3, [r5], #4 b .L216 .L141: ldr r3, [sp, #4] ldr r2, [r4, #0] cmp ip, #1 movls r3, #0 andhi r3, r3, #1 cmp r3, #0 ldreqb r3, [r2, lr] @ zero_extendqisi2 add r0, r5, #4 subeq ip, ip, #1 streq r3, [r5, #0] beq .L214 ldrh r3, [r2, #8] sub ip, ip, #2 mov r3, r3, asl #16 mov r1, r3, lsr #16 and r2, r1, #255 mov r3, r3, lsr #24 str r3, [r5, #0] str r2, [r0], #4 .L214: mov r5, r0 b .L216 .L138: cmp sl, #4 bne .L112 mov r0, #0 .L155: ldr r2, [r4, #168] ldr r3, .L217 add r1, r2, #1 cmp r2, r3 bhi .L157 ldr r2, [r4, #0] mvn r3, #96 str r1, [r4, #168] cmp r8, #0 strb r3, [r2, #0] ldrne r3, [r4, #0] mvn r1, #64 ldrneb r3, [r3, #0] @ zero_extendqisi2 ldr r3, [r4, #0] ldrb r2, [r3, #0] @ zero_extendqisi2 strb r1, [r3, #0] and r2, r2, #1 ldrne r3, [r4, #0] orr r0, r2, r0, asl #1 and r2, r0, #7 ldrneb r3, [r3, #0] @ zero_extendqisi2 cmp r2, #7 bne .L155 b .L156 .L112: cmp sl, #6 ldreq r3, [r4, #4] biceq r3, r3, #3 streq r3, [r4, #4] beq .L157 .L156: cmp sl, #5 bne .L157 ldmia r4, {r2, r3} @ phole ldm orr r3, r3, #2 mvn r0, #32 str r3, [r4, #4] cmp r8, #0 strb r0, [r2, #0] ldrne r3, [r4, #0] mvn r1, #0 ldrneb r2, [r3, #0] @ zero_extendqisi2 ldrneb r3, [r3, #0] @ zero_extendqisi2 ldr r3, [r4, #0] strb r1, [r3, #0] ldrne r3, [r4, #0] ldrneb r2, [r3, #0] @ zero_extendqisi2 ldrneb r3, [r3, #0] @ zero_extendqisi2 ldr r3, [r4, #0] strb r0, [r3, #0] ldrne r3, [r4, #0] ldrneb r2, [r3, #0] @ zero_extendqisi2 ldrneb r3, [r3, #0] @ zero_extendqisi2 ldr r3, [r4, #0] strb r1, [r3, #0] ldrne r3, [r4, #0] ldrneb r2, [r3, #0] @ zero_extendqisi2 ldrneb r3, [r3, #0] @ zero_extendqisi2 ldmia r4, {r2, r3} @ phole ldm tst r3, #32 movne r3, #16 moveq r3, #30 strb r3, [r2, #0] cmp r8, #0 ldrne r3, [r4, #0] ldrneb r2, [r3, #0] @ zero_extendqisi2 ldrneb r3, [r3, #0] @ zero_extendqisi2 ldmia r4, {r2, r3} @ phole ldm tst r3, #32 movne r3, #48 moveq r3, #62 strb r3, [r2, #0] cmp r8, #0 ldrne r3, [r4, #0] ldrneb r2, [r3, #0] @ zero_extendqisi2 ldrneb r3, [r3, #0] @ zero_extendqisi2 .L157: cmp sl, #7 cmpne sl, #0 ldreq r3, [r4, #4] orreq r3, r3, #1 streq r3, [r4, #4] .L109: ldr r3, [r4, #4] tst r3, #3 bne .L175 cmp r8, #0 beq .L176 mov r6, #7 .L180: ldr r2, [r4, #0] mvn r3, #32 strb r3, [r2, #0] ldr r3, [r4, #0] ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 mvn r2, #0 strb r2, [r3, #0] ldr r3, [r4, #0] adds r6, r6, r2 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r3, [r3, #0] @ zero_extendqisi2 bpl .L180 b .L175 .L176: ldr r3, [r4, #0] mvn r2, #0 strb r2, [r3, #0] ldr r3, [r4, #0] strb r2, [r3, #8] .L175: ldr r2, [r4, #168] ldr r3, .L217 cmp r2, r3 addls r3, r2, #1 strls r3, [r4, #168] movls r0, #0 bls .L74 .L213: mov r0, #1 .L74: add sp, sp, #84 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} bx lr .L218: .align 2 .L217: .word 1000000 .word 100001 .size sdcmd2, .-sdcmd2 .section .text.stop2,"ax",%progbits .align 2 .type stop2, %function stop2: @ Function supports interworking. @ args = 0, pretend = 0, frame = 24 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, lr} ldr r3, [r0, #172] sub sp, sp, #32 cmp r3, #0 mov r4, r0 beq .L220 ldr r3, [r0, #28] cmp r3, #0 ldrne r0, [r0, #12] movne r1, #0 movne lr, pc bxne r3 .L221: ldr r3, [r4, #4] add r1, sp, #8 ands ip, r3, #2 beq .L222 mov r5, #0 mov r3, r1 mov r0, r4 ldr r1, .L231 mov r2, r5 str r5, [sp, #0] bl sdcmd2 ldr r3, [r4, #0] mov r6, r0 strb r5, [r3, #12] ldr r3, [r4, #28] cmp r3, r5 ldrne r0, [r4, #12] movne r1, #5 movne lr, pc bxne r3 .L223: ldr r2, [r4, #0] mvn r3, #0 strb r3, [r2, #0] str r5, [r4, #168] b .L225 .L222: mov r3, r1 mov r2, ip mov r0, r4 ldr r1, .L231 str ip, [sp, #0] bl sdcmd2 mov r6, r0 .L225: mov r3, #0 cmp r6, #0 str r3, [r4, #172] bne .L227 add r0, sp, #8 ldr r1, .L231 bl error cmp r0, #0 bne .L227 ldr r2, [r4, #168] ldr r3, .L231+4 cmp r2, r3 addls r3, r2, #1 strls r3, [r4, #168] bls .L220 .L227: mov r0, #1 b .L219 .L220: mov r0, #0 .L219: add sp, sp, #32 ldmfd sp!, {r4, r5, r6, lr} bx lr .L232: .align 2 .L231: .word 1612 .word 1000000 .size stop2, .-stop2 .section .text.activate,"ax",%progbits .align 2 .type activate, %function activate: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, lr} ldr r3, [r0, #4] mov r4, r0 and r3, r3, #1536 cmp r3, #512 moveq r0, #0 beq .L233 mov r5, #0 .L240: ldr r6, .L248 ldr r1, [r6, r5, asl #2] cmp r1, #0 beq .L236 ldr r2, [r1, #0] ldr r3, [r4, #0] cmp r2, r3 bne .L237 ldr r3, [r1, #4] tst r3, #512 bne .L236 .L237: add r5, r5, #1 cmp r5, #255 bls .L240 .L236: ldr r0, [r6, r5, asl #2] cmp r0, #0 beq .L241 bl stop2 ldr r2, [r6, r5, asl #2] ldr r3, [r2, #4] bic r3, r3, #512 str r3, [r2, #4] .L241: ldr r2, [r4, #4] ldr r3, [r4, #64] ldr r1, [r4, #0] tst r2, #128 strh r3, [r1, #2] @ movhi movne r3, #56 moveq r3, #24 strb r3, [r1, #1] ldr r3, [r4, #4] orr r3, r3, #512 ands r2, r3, #1024 str r3, [r4, #4] moveq r0, r2 movne r0, #1 .L233: ldmfd sp!, {r4, r5, r6, lr} bx lr .L249: .align 2 .L248: .word sdcores .size activate, .-activate .section .text.sdcmd,"ax",%progbits .align 2 .type sdcmd, %function sdcmd: @ Function supports interworking. @ args = 4, pretend = 0, frame = 80 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} mov r4, r0 ldr r0, [r0, #176] sub sp, sp, #92 mov r1, r1, asl #16 add fp, sp, #16 cmp r0, #0 mov sl, r1, lsr #24 str fp, [sp, #12] mov lr, r2 mov r8, r3 mov r9, r1, lsr #16 beq .L251 ldr ip, [sp, #128] mov r0, r4 mov r1, r9 str ip, [sp, #0] bl sdcmd2 b .L250 .L251: cmp r3, #0 moveq r8, fp ldr r0, [r4, #0] str r8, [sp, #8] .L346: ldrb r2, [r0, #2] @ zero_extendqisi2 and r3, r2, #7 cmp r3, #1 and r5, r2, #255 beq .L254 ldr r2, [r4, #168] ldr r3, .L350 add r1, r2, #1 cmp r2, r3 strls r1, [r4, #168] bls .L346 .L254: mov r3, sl, asl #5 orr r2, r3, #1 and r3, r5, #231 cmp r3, r2 ldrne r3, [r4, #0] mov r1, lr, lsr #8 strneb r2, [r3, #2] ldr r0, [sp, #12] mov r3, lr, lsr #24 mov r2, lr, lsr #16 mov ip, #0 str lr, [r0, #16] str r3, [r0, #4] str r2, [r0, #8] str r1, [r0, #12] str r9, [r0, #0] mov lr, r0 mov r7, ip .L269: ldrb r1, [lr, #0] @ zero_extendqisi2 mov r6, #0 .L268: add r3, r6, #1 mov ip, ip, asl #1 and r6, r3, #255 eor r3, r1, ip tst r3, #128 mov r2, r1, asl #1 eorne ip, ip, #9 cmp r6, #7 and r1, r2, #255 bls .L268 add r7, r7, #1 cmp r7, #5 and ip, ip, #127 add lr, lr, #4 bcc .L269 mov r3, ip, asl #1 orr r3, r3, #1 str r3, [r0, #20] ldr r2, [r4, #4] rsb r3, fp, r0 mov r3, r3, asr #2 orr r2, r2, #8 cmp r3, #6 str r2, [r4, #4] .L347: beq .L273 ldr ip, [r4, #168] ldr r3, .L350 mov r0, r4 cmp ip, r3 add r1, sp, #12 ldr r2, [sp, #128] add lr, ip, #1 bhi .L273 str lr, [r4, #168] bl tend_ssp ldr r3, [sp, #12] mov r5, r0 rsb r3, fp, r3 mov r3, r3, asr #2 cmp r3, #6 b .L347 .L273: ldr r3, [r4, #4] and r2, r5, #7 bic r3, r3, #8 cmp r2, #1 str r3, [r4, #4] bne .L345 cmp sl, #1 beq .L281 cmp sl, #3 movne r7, #6 moveq r7, #17 .L292: ldr r1, [r4, #168] ldr r3, .L350 add ip, r1, #1 cmp r1, r3 mov r0, r4 ldr r2, [sp, #128] add r3, ip, #1000 bhi .L286 cmp r9, #584 str ip, [r4, #168] mov r1, #0 streq r3, [r4, #168] bl tend_ssp and r3, r0, #7 sub r3, r3, #2 cmp r3, #1 mov r5, r0 bhi .L292 .L286: ldr r3, [r4, #4] tst r3, #3 beq .L293 .L294: ldr ip, [r4, #168] ldr r3, .L350 mov r0, r4 cmp ip, r3 mov r1, #0 ldr r2, [sp, #128] add lr, ip, #1 bhi .L295 str lr, [r4, #168] bl tend_ssp tst r0, #24 mov r5, r0 beq .L294 .L295: and r3, r5, #7 cmp r3, #3 mov r6, #0 beq .L293 .L309: ldr r1, [r4, #168] ldr r3, .L350 mov r0, r4 cmp r1, r3 ldr r2, [sp, #128] add ip, r1, #1 bhi .L302 cmp r6, #2 str ip, [r4, #168] mov r1, #0 bhi .L345 bl tend_ssp tst r0, #16 and r3, r0, #7 addne r6, r6, #1 cmp r3, #3 mov r5, r0 bne .L309 .L302: cmp r6, #2 bls .L293 .L345: ldr r2, [r4, #0] mov r3, #7 mov r0, #1 strb r3, [r2, #2] b .L250 .L293: ldr r3, [r4, #4] cmp sl, #0 bic r3, r3, #3 str r3, [r4, #4] orreq r3, r3, #1 streq r3, [r4, #4] ldr r2, [r4, #4] ldr r3, [sp, #8] orr r2, r2, #4 rsb r3, r8, r3 cmp r7, r3, asr #2 str r2, [r4, #4] .L348: beq .L313 ldr ip, [r4, #168] ldr r3, .L350 mov r0, r4 cmp ip, r3 add r1, sp, #8 ldr r2, [sp, #128] add lr, ip, #1 bhi .L313 str lr, [r4, #168] bl tend_ssp tst r0, #16 mov r5, r0 beq .L312 ldr r3, [sp, #8] cmp r8, r3 beq .L336 .L312: ldr r3, [sp, #8] rsb r3, r8, r3 cmp r7, r3, asr #2 b .L348 .L313: ldr r3, [r4, #4] cmp sl, #6 bic r2, r3, #4 str r2, [r4, #4] biceq r3, r3, #7 beq .L349 cmp sl, #5 bne .L281 orr r3, r2, #2 .L349: str r3, [r4, #4] .L281: ldr r2, [r4, #168] ldr r3, .L350 cmp r2, r3 movhi r0, #1 bhi .L250 b .L323 .L336: ldr r2, [r4, #0] mov r3, #7 strb r3, [r2, #2] ldr r3, [r4, #4] mov r0, #1 bic r3, r3, #5 str r3, [r4, #4] b .L250 .L323: add r3, r2, #1 str r3, [r4, #168] mov r0, #0 .L250: add sp, sp, #92 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} bx lr .L351: .align 2 .L350: .word 1000000 .size sdcmd, .-sdcmd .section .text.datssp_stream2,"ax",%progbits .align 2 .type datssp_stream2, %function datssp_stream2: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, sl, lr} mov r6, r0 sub sp, sp, #4 mov sl, r1 mov r4, r2 .L359: ldr ip, [r6, #16] ldr r5, [sl, #0] cmp ip, #0 beq .L353 ldr r3, [r6, #4] tst r3, #1 beq .L353 ldr r0, [r6, #12] mov r1, r5 mov r2, r4 mov lr, pc bx ip rsbs r3, r0, #1 movcc r3, #0 cmp r5, #0 moveq r3, #0 cmp r3, #0 ldrne r3, [sl, #0] addne r3, r3, r4 strne r3, [sl, #0] b .L352 .L353: cmp r4, #512 .L425: bls .L409 mov r1, sl mov r2, #512 mov r0, r6 bl datssp_stream2 ldr r3, [r6, #28] sub r4, r4, #512 cmp r3, #0 mov r1, #1 ldrne r0, [r6, #12] movne lr, pc bxne r3 .L360: ldr r5, [sl, #0] cmp r4, #512 b .L425 .L409: ldr r3, [r6, #176] mov r8, #0 cmp r3, #2 movne r7, #0 moveq r7, #1 cmp r7, r8 bne .L363 cmp r3, #3 bne .L362 .L363: mov r8, #1 .L362: ldr r3, [r6, #4] bics r2, r8, r7 moveq lr, #4 movne lr, #5 tst r3, #1 and r3, r5, #1 beq .L366 cmp r4, #1 orreq r3, r3, #1 cmp r3, #0 beq .L411 .L369: ldr r3, [r6, #0] sub r4, r4, #1 ldrb r3, [r3, lr] @ zero_extendqisi2 strb r3, [r5], #1 cmp r4, #1 movne r3, r5 orreq r3, r5, #1 tst r3, #1 bne .L369 .L411: cmp r4, #1 movls r3, #0 movhi r3, #1 ands r3, r3, r5, lsr #1 beq .L370 ldr r0, [r6, #0] cmp r8, #0 ldreqb r2, [r0, lr] @ zero_extendqisi2 ldreqb r3, [r0, lr] @ zero_extendqisi2 ldrneh r3, [r0, #4] add r1, r5, #2 orreq ip, r2, r3, asl #8 strneh r3, [r5, #0] @ movhi streqh ip, [r5, #0] @ movhi sub r4, r4, #2 mov r5, r1 .L370: cmp r7, #0 beq .L373 cmp r4, #3 .L426: bls .L386 ldr r3, [r6, #0] sub r4, r4, #4 ldr r3, [r3, #4] cmp r4, #3 str r3, [r5], #4 b .L426 .L373: cmp r8, #0 beq .L378 cmp r4, #3 .L427: bls .L386 ldr r3, [r6, #0] sub r4, r4, #4 ldrh r2, [r3, #4] ldrh r3, [r3, #4] cmp r4, #3 orr ip, r2, r3, asl #16 str ip, [r5], #4 b .L427 .L378: cmp r4, #3 .L428: bls .L386 ldr r3, [r6, #0] sub r4, r4, #4 ldrb r1, [r3, lr] @ zero_extendqisi2 ldrb r2, [r3, lr] @ zero_extendqisi2 ldrb r0, [r3, lr] @ zero_extendqisi2 orr ip, r1, r2, asl #8 ldrb r3, [r3, lr] @ zero_extendqisi2 orr ip, ip, r0, asl #16 orr ip, ip, r3, asl #24 cmp r4, #3 str ip, [r5], #4 b .L428 .L366: cmp r4, #1 orreq r3, r3, #1 cmp r3, #0 beq .L419 .L389: ldrb r3, [r5], #1 @ zero_extendqisi2 sub r4, r4, #1 cmp r4, #1 movne r2, r5 orreq r2, r5, #1 ldr r1, [r6, #0] tst r2, #1 strb r3, [r1, #4] bne .L389 .L419: cmp r4, #1 movls r3, #0 movhi r3, #1 ands r3, r3, r5, lsr #1 beq .L390 ldrh r3, [r5, #0] cmp r8, #0 ldr r0, [r6, #0] moveq r3, r3, asl #16 moveq ip, r3, lsr #16 streqb ip, [r0, #4] ldreq r2, [r6, #0] add r1, r5, #2 moveq r3, r3, lsr #24 sub r4, r4, #2 strneh r3, [r0, #4] @ movhi streqb r3, [r2, #4] mov r5, r1 .L390: cmp r7, #0 beq .L393 cmp r4, #3 .L429: bls .L386 sub r4, r4, #4 ldr r2, [r6, #0] ldr r3, [r5], #4 cmp r4, #3 str r3, [r2, #4] b .L429 .L393: cmp r8, #0 beq .L398 cmp r4, #3 bls .L386 ldr r2, [r6, #0] .L401: ldr ip, [r5], #4 sub r4, r4, #4 mov r3, ip, lsr #16 cmp r4, #3 strh ip, [r2, #4] @ movhi strh r3, [r2, #4] @ movhi bhi .L401 b .L386 .L398: cmp r4, #3 .L430: bls .L386 ldr ip, [r5], #4 ldr r3, [r6, #0] mov r2, ip, lsr #8 strb ip, [r3, #4] ldr r3, [r6, #0] mov r1, ip, lsr #16 strb r2, [r3, #4] ldr r3, [r6, #0] sub r4, r4, #4 strb r1, [r3, #4] ldr r2, [r6, #0] mov r3, ip, lsr #24 cmp r4, #3 strb r3, [r2, #4] b .L430 .L386: cmp r4, #0 str r5, [sl, #0] bne .L359 mov r0, r4 .L352: add sp, sp, #4 ldmfd sp!, {r4, r5, r6, r7, r8, sl, lr} bx lr .size datssp_stream2, .-datssp_stream2 .section .text.datssp_stream,"ax",%progbits .align 2 .type datssp_stream, %function datssp_stream: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, lr} ldr r3, [r0, #4] sub sp, sp, #4 tst r3, #1 mov r6, r0 mov r7, r1 mov r4, r2 mov r5, #0 beq .L432 ldr r3, [r0, #16] cmp r3, r5 beq .L432 cmp r1, r5 ldrne r5, [r1, #0] moveq r5, r1 ldr r0, [r0, #12] mov r1, r5 mov lr, pc bx r3 rsbs r3, r0, #1 movcc r3, #0 cmp r5, #0 moveq r3, #0 cmp r3, #0 ldrne r3, [r7, #0] addne r3, r3, r4 strne r3, [r7, #0] b .L431 .L432: ldr r3, [r6, #176] cmp r3, #0 beq .L485 mov r0, r6 mov r1, r7 mov r2, r4 add sp, sp, #4 ldmfd sp!, {r4, r5, r6, r7, lr} b datssp_stream2 .L485: cmp r4, #0 beq .L446 ldr ip, [r6, #168] ldr r3, .L486 mov r0, r6 cmp ip, r3 mov r1, #0 mov r2, r7 add lr, ip, #1 movhi r0, #1 bhi .L431 .L440: str lr, [r6, #168] bl tend_ssp tst r0, #16 beq .L485 cmp r5, #7 sub r4, r4, #1 add r5, r5, #1 bls .L485 ldr r3, [r6, #4] tst r3, #1 beq .L448 .L446: cmp r7, #0 beq .L450 cmp r4, #0 ldr r5, [r7, #0] beq .L479 .L453: ldr r3, [r6, #0] subs r4, r4, #1 ldrb r3, [r3, #1] @ zero_extendqisi2 strb r3, [r5], #1 bne .L453 b .L479 .L450: subs r4, r4, #1 bcc .L466 ldr r0, [r6, #0] .L457: sub r4, r4, #1 cmn r4, #1 ldrb r3, [r0, #1] @ zero_extendqisi2 bne .L457 b .L466 .L448: cmp r7, #0 beq .L458 ldr r5, [r7, #0] cmp r4, #0 .L483: beq .L479 ldr r3, [r6, #0] ldrb r2, [r5], #1 @ zero_extendqisi2 sub r4, r4, #1 strb r2, [r3, #1] ldr r3, [r6, #4] tst r3, #16 bne .L459 tst r3, #32 mov r1, r2 mov r0, r6 beq .L462 bl sd_4bit_feedcrc b .L459 .L462: mov r1, r2 mov r0, r6 bl sd_1bit_feedcrc .L459: cmp r4, #0 b .L483 .L479: str r5, [r7, #0] b .L466 .L458: sub r4, r4, #1 .L484: cmn r4, #1 beq .L466 ldr r3, [r6, #4] ldr r5, [r6, #0] tst r3, #16 mov r0, #0 bne .L469 tst r3, #32 mov r0, r6 beq .L470 bl sd_4bit_getcrc b .L469 .L470: mov r0, r6 bl sd_1bit_getcrc .L469: sub r4, r4, #1 strb r0, [r5, #1] b .L484 .L466: mov r0, #0 .L431: add sp, sp, #4 ldmfd sp!, {r4, r5, r6, r7, lr} bx lr .L487: .align 2 .L486: .word 1000000 .size datssp_stream, .-datssp_stream .section .text.stop,"ax",%progbits .align 2 .type stop, %function stop: @ Function supports interworking. @ args = 0, pretend = 0, frame = 24 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, lr} ldr r3, [r0, #176] sub sp, sp, #32 cmp r3, #0 mov r4, r0 beq .L489 bl stop2 b .L488 .L489: ldr r3, [r0, #172] cmp r3, #0 beq .L490 ldmia r0, {r0, r3} @ phole ldm ands ip, r3, #2 beq .L491 .L507: ldrb r3, [r0, #2] @ zero_extendqisi2 and r3, r3, #7 cmp r3, #5 beq .L493 ldr r2, [r4, #168] ldr r3, .L508 add r1, r2, #1 cmp r2, r3 strls r1, [r4, #168] bls .L507 .L493: ldr r2, [r4, #0] mvn r3, #62 strb r3, [r2, #2] ldr r3, [r4, #4] mov ip, #0 bic r3, r3, #2 orr r3, r3, #1 str r3, [r4, #4] mov r2, ip add r3, sp, #8 mov r0, r4 ldr r1, .L508+4 str ip, [sp, #0] bl sdcmd ldmia r4, {r2, r3} @ phole ldm bic r3, r3, #1 str r3, [r4, #4] mvn r3, #123 strb r3, [r2, #2] b .L499 .L491: mvn r3, #62 strb r3, [r0, #2] mov r2, ip mov r0, r4 ldr r1, .L508+4 add r3, sp, #8 str ip, [sp, #0] bl sdcmd .L499: mov r3, #0 cmp r0, #0 str r3, [r4, #172] bne .L501 add r0, sp, #8 ldr r1, .L508+4 bl error cmp r0, #0 bne .L501 ldr r2, [r4, #168] ldr r3, .L508 cmp r2, r3 addls r3, r2, #1 strls r3, [r4, #168] bls .L490 .L501: mov r0, #1 b .L488 .L490: mov r0, #0 .L488: add sp, sp, #32 ldmfd sp!, {r4, lr} bx lr .L509: .align 2 .L508: .word 1000000 .word 1612 .size stop, .-stop .section .text.do_read2,"ax",%progbits .align 2 .type do_read2, %function do_read2: @ Function supports interworking. @ args = 0, pretend = 0, frame = 8 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, lr} subs sl, r3, #0 sub sp, sp, #16 mov r4, r0 mov r7, r1 mov r8, r2 beq .L531 bl activate cmp r0, #0 mov r6, r0 bne .L539 ldr r3, [r8, #0] mov r0, r4 str r3, [sp, #12] ldr r5, [r8, #4] bl sdsize cmp r7, r0 mov r9, r0 movcs r0, r6 bcs .L510 ldr r2, [r4, #172] cmp r2, #0 beq .L514 ldr r3, [r4, #4] tst r3, #2 bne .L515 cmp r2, r7 bne .L515 ldr r2, [r4, #28] cmp r2, #0 beq .L517 ldr r3, [r4, #16] cmp r3, #0 bne .L517 ldr r0, [r4, #12] mov r1, #3 mov lr, pc bx r2 b .L517 .L515: mov r0, r4 bl stop2 .L514: ldr r3, [r4, #4] ands ip, r3, #64 movne ip, #0 movne r3, ip movne r0, r4 ldrne r1, .L541 movne r2, r7 moveq r3, ip moveq r0, r4 ldreq r1, .L541 moveq r2, r7, asl #9 str ip, [sp, #0] bl sdcmd2 .L520: ldr r2, [r4, #168] ldr r3, .L541+4 add r1, r2, #1 cmp r2, r3 bls .L524 .L539: mov r0, #1 b .L510 .L524: ldr r2, [r4, #0] mvn r3, #32 str r1, [r4, #168] strb r3, [r2, #0] ldr r2, [r4, #0] add r3, r3, #32 ldrb r1, [r2, #0] @ zero_extendqisi2 strb r3, [r2, #0] ands r1, r1, #15 bne .L520 str r1, [r4, #168] .L517: ldr ip, [r4, #20] cmp ip, #0 beq .L528 ldr r3, [r4, #16] cmp r3, #0 ldrne r0, [r4, #12] ldrne r1, [sp, #12] movne r2, r5, asl #9 movne lr, pc bxne ip .L528: ldr r3, [r4, #0] add r1, r7, r5 mvn r2, #32 strb r2, [r3, #0] str r1, [r4, #172] .L529: .L540: ldr r3, [r4, #172] add r1, sp, #12 cmp r3, r9 rsb r3, r9, r3 rsbhi r5, r3, r5 strhi r9, [r4, #172] mov r0, r4 mov r2, r5, asl #9 bl datssp_stream2 subs sl, sl, #1 add r8, r8, #8 beq .L531 ldr r5, [r8, #4] ldr r3, [r4, #172] ldr ip, [r4, #20] ldr r1, [r8, #0] add r3, r3, r5 cmp ip, #0 str r3, [r4, #172] str r1, [sp, #12] beq .L540 ldr r3, [r4, #16] mov r2, r5, asl #9 cmp r3, #0 beq .L540 ldr r0, [r4, #12] mov lr, pc bx ip b .L540 .L531: mov r0, sl .L510: add sp, sp, #16 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, lr} bx lr .L542: .align 2 .L541: .word 1874 .word 1000000 .size do_read2, .-do_read2 .section .text.do_read,"ax",%progbits .align 2 .type do_read, %function do_read: @ Function supports interworking. @ args = 0, pretend = 0, frame = 32 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} subs r9, r3, #0 sub sp, sp, #44 mov r4, r0 mov r7, r1 mov sl, r2 beq .L569 ldr r8, [r2, #0] ldr r5, [r2, #4] str r8, [sp, #12] bl sdsize cmp r7, r0 mov r6, r0 movcs r0, #0 bcs .L543 ldr r2, [r4, #172] cmp r2, #0 beq .L546 ldr r3, [r4, #4] tst r3, #2 bne .L547 cmp r2, r7 beq .L548 .L547: mov r0, r4 bl stop .L546: ldr r3, [r4, #4] add r2, sp, #16 tst r3, #64 movne r3, r2 moveq r3, r2 add ip, sp, #12 movne r0, r4 movne r1, #82 movne r2, r7 moveq r0, r4 moveq r1, #82 moveq r2, r7, asl #9 str ip, [sp, #0] bl sdcmd cmp r0, #0 bne .L552 add r0, sp, #16 mov r1, #82 bl error cmp r0, #0 beq .L548 .L552: mov r0, #1 b .L543 .L548: ldr ip, [r4, #20] cmp ip, #0 beq .L553 ldr r3, [r4, #16] cmp r3, #0 ldrne r1, [sp, #12] ldrne r0, [r4, #12] rsbne r2, r8, r1 rsbne r2, r2, r5, asl #9 movne lr, pc bxne ip .L553: ldr r2, [sp, #12] add fp, sp, #12 rsb r2, r8, r2 rsb r2, r2, #512 mov r1, fp mov r0, r4 bl datssp_stream mov r1, #0 mov r0, r4 mov r2, #6 bl datssp_stream add r1, r7, r5 cmp r1, r6 rsbhi r3, r6, r1 rsbhi r5, r3, r5 str r1, [r4, #172] sub r5, r5, #1 strhi r6, [r4, #172] .L555: .L570: sub r5, r5, #1 .L568: cmn r5, #1 beq .L563 ldr r3, [r4, #0] mov r2, #2 strb r2, [r3, #2] mov r1, #0 mov r0, r4 bl datssp_stream mov r1, fp mov r0, r4 mov r2, #512 bl datssp_stream mov r0, r4 mov r1, #0 mov r2, #6 sub r5, r5, #1 bl datssp_stream b .L568 .L563: subs r9, r9, #1 beq .L559 add sl, sl, #8 ldr r5, [sl, #4] ldr r3, [r4, #172] ldr ip, [r4, #20] add r3, r3, r5 cmp r3, r6 str r3, [r4, #172] ldr r2, [sl, #0] rsbhi r3, r6, r3 rsbhi r5, r3, r5 strhi r6, [r4, #172] cmp ip, #0 str r2, [sp, #12] beq .L570 ldr r3, [r4, #16] cmp r3, #0 cmpne r5, #0 beq .L570 ldr r0, [r4, #12] ldr r1, [sp, #12] mov r2, r5, asl #9 mov lr, pc bx ip b .L570 .L559: ldr r3, [r4, #0] mov r2, #2 strb r2, [r3, #2] mov r0, r4 mov r1, r9 bl datssp_stream .L569: mov r0, r9 .L543: add sp, sp, #44 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} bx lr .size do_read, .-do_read .section .text.do_write2,"ax",%progbits .align 2 .type do_write2, %function do_write2: @ Function supports interworking. @ args = 0, pretend = 0, frame = 32 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, sl, lr} mov r5, r0 ldr r0, [r0, #36] sub sp, sp, #44 cmp r0, #0 mov r7, r1 mov sl, r2 mov r6, r3 bne .L587 cmp r3, #0 moveq r0, r3 beq .L571 mov r0, r5 bl activate cmp r0, #0 mov r4, r0 bne .L587 mov r0, r5 bl sdsize cmp r7, r0 mov r8, r0 movcs r0, r4 bcs .L571 ldr r3, [r5, #32] cmp r3, #0 beq .L576 mov r0, r5 mov lr, pc bx r3 cmp r0, #0 bne .L576 ldr r3, [r5, #172] cmp r3, #0 beq .L587 mov r0, r5 bl stop2 b .L587 .L576: ldr r2, [r5, #172] cmp r2, #0 beq .L580 ldr r3, [r5, #4] tst r3, #2 beq .L581 cmp r2, r7 beq .L582 .L581: mov r0, r5 bl stop2 .L580: ldr r3, [r5, #8] cmp r3, #0 beq .L583 mov r4, #0 ldr r2, [r5, #68] ldr r1, .L601 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd2 ldr r2, [r5, #8] mov r0, r5 ldr r1, .L601+4 mov r3, r4 str r4, [sp, #0] bl sdcmd2 str r4, [r5, #8] .L583: ldr r3, [r5, #4] add r2, sp, #16 ands ip, r3, #64 movne r3, r2 movne ip, #0 moveq r3, r2 movne r0, r5 ldrne r1, .L601+8 movne r2, r7 moveq r0, r5 ldreq r1, .L601+8 moveq r2, r7, asl #9 str ip, [sp, #0] bl sdcmd2 cmp r0, #0 bne .L587 add r0, sp, #16 ldr r1, .L601+8 bl error cmp r0, #0 ldreq r3, [r5, #0] streq r7, [r5, #172] ldreqb r3, [r3, #1] @ zero_extendqisi2 beq .L582 .L587: mov r0, #1 b .L571 .L582: sub r6, r6, #1 .L600: cmn r6, #1 beq .L598 ldr ip, [sl, #4] ldr r3, [r5, #172] ldr r2, [sl, #0] add r3, r3, ip cmp r3, r8 rsb lr, r8, r3 rsbhi ip, lr, ip str r2, [sp, #12] str r3, [r5, #172] mov r0, r5 add r1, sp, #12 strhi r8, [r5, #172] mov r2, ip, asl #9 sub r6, r6, #1 add sl, sl, #8 bl datssp_stream2 b .L600 .L598: ldr r3, [r5, #60] cmp r3, #0 bne .L592 mov r0, r5 bl stop2 cmp r0, #0 bne .L571 .L592: ldr r3, [r5, #28] cmp r3, #0 ldrne r0, [r5, #12] movne r1, #2 movne lr, pc bxne r3 .L594: ldr r3, [r5, #0] ldrb r3, [r3, #1] @ zero_extendqisi2 ands r0, r3, #68 ldrne r3, .L601+12 movne r0, #1 strne r3, [r5, #168] .L571: add sp, sp, #44 ldmfd sp!, {r4, r5, r6, r7, r8, sl, lr} bx lr .L602: .align 2 .L601: .word 631 .word 599 .word 1369 .word 1000001 .size do_write2, .-do_write2 .section .text.do_write,"ax",%progbits .align 2 .type do_write, %function do_write: @ Function supports interworking. @ args = 0, pretend = 0, frame = 32 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, sl, lr} ldr r4, [r0, #36] sub sp, sp, #44 cmp r4, #0 mov r5, r0 mov r7, r1 mov sl, r2 mov r6, r3 bne .L616 cmp r3, #0 moveq r0, r3 beq .L603 mov r0, r5 bl sdsize cmp r7, r0 mov r8, r0 movcs r0, r4 bcs .L603 ldr r2, [r5, #4] ldr r1, [r5, #172] bic r3, r2, #16 cmp r1, #0 str r3, [r5, #4] beq .L609 tst r2, #2 beq .L610 cmp r1, r7 beq .L611 .L610: mov r0, r5 bl stop .L609: ldr r3, [r5, #8] cmp r3, #0 beq .L612 mov r4, #0 ldr r2, [r5, #68] ldr r1, .L632 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd ldr r2, [r5, #8] mov r0, r5 ldr r1, .L632+4 mov r3, r4 str r4, [sp, #0] bl sdcmd str r4, [r5, #8] .L612: ldr r3, [r5, #4] add r2, sp, #16 ands ip, r3, #64 movne r3, r2 movne ip, #0 moveq r3, r2 movne r0, r5 ldrne r1, .L632+8 movne r2, r7 moveq r0, r5 ldreq r1, .L632+8 moveq r2, r7, asl #9 str ip, [sp, #0] bl sdcmd cmp r0, #0 bne .L616 add r0, sp, #16 ldr r1, .L632+8 bl error cmp r0, #0 streq r7, [r5, #172] beq .L611 .L616: mov r0, #1 b .L603 .L611: sub r6, r6, #1 cmn r6, #1 .L630: beq .L626 ldr r4, [sl, #4] ldr r3, [r5, #172] ldr r2, [sl, #0] add r3, r3, r4 cmp r3, r8 str r3, [r5, #172] rsbhi r3, r8, r3 rsbhi r4, r3, r4 sub r4, r4, #1 strhi r8, [r5, #172] str r2, [sp, #12] cmn r4, #1 .L631: beq .L628 add r1, sp, #12 mov r2, #512 mov r0, r5 bl datssp_stream mov r2, #8 mov r0, r5 mov r1, #0 bl datssp_stream sub r4, r4, #1 ldr r2, [r5, #0] mvn r3, #89 cmn r4, #1 strb r3, [r2, #2] b .L631 .L628: sub r6, r6, #1 cmn r6, #1 add sl, sl, #8 b .L630 .L626: ldr r3, [r5, #60] cmp r3, #0 moveq r0, r5 bleq stop .L624: mov r0, #0 .L603: add sp, sp, #44 ldmfd sp!, {r4, r5, r6, r7, r8, sl, lr} bx lr .L633: .align 2 .L632: .word 631 .word 599 .word 1369 .size do_write, .-do_write .section .text.version,"ax",%progbits .align 2 .type version, %function version: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 str lr, [sp, #-4]! mov r1, #0 mov lr, r0 .L640: ldr r3, .L649 ldr r0, [r3, r1, asl #2] add r1, r1, #1 cmp r0, #0 beq .L636 ldr r2, [r0, #0] ldr r3, [lr, #0] cmp r2, r3 beq .L648 cmp r1, #255 bls .L640 .L636: ldr r2, [lr, #0] ldrb r1, [r2, #3] @ zero_extendqisi2 and ip, r1, #255 eor r3, ip, #64 strb r3, [r2, #3] ldr r2, [lr, #0] and r1, r1, #64 ldrb r3, [r2, #3] @ zero_extendqisi2 strb ip, [r2, #3] and r3, r3, #64 cmp r1, r3 movne r0, #0 bne .L634 cmp r1, #0 movne r0, #1 bne .L634 ldr r0, [lr, #0] ldr ip, [r0, #12] ldrh r3, [r0, #12] tst ip, #64 beq .L644 tst r3, #64 movne r0, #2 bne .L634 .L644: ldrb r3, [r0, #12] @ zero_extendqisi2 tst r3, #64 movne r0, #3 bne .L634 b .L645 .L648: ldr r0, [r0, #176] b .L634 .L645: mov r0, #4 .L634: ldr lr, [sp], #4 bx lr .L650: .align 2 .L649: .word sdcores .size version, .-version .section .text.sdlockctl2,"ax",%progbits .align 2 .type sdlockctl2, %function sdlockctl2: @ Function supports interworking. @ args = 0, pretend = 0, frame = 48 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} mov r5, r0 ldr r0, [r0, #96] ldr ip, [r5, #92] mov r0, r0, lsr #4 orr r0, r0, ip, asl #4 sub sp, sp, #60 tst r0, #128 mov r8, r1 mov r7, r2 mov r9, r3 add fp, sp, #32 beq .L735 rsbs r6, r2, #1 movcc r6, #0 cmp r1, #8 moveq r6, #0 cmp r6, #0 bne .L735 mov r0, r5 bl stop2 ldr r3, [r5, #4] ands r2, r3, #32 beq .L654 ldr r2, [r5, #68] ldr r1, .L736 mov r3, r6 mov r0, r5 str r6, [sp, #0] bl sdcmd2 ldr r1, .L736+4 mov r2, r6 mov r3, r6 mov r0, r5 str r6, [sp, #0] bl sdcmd2 ldr r3, [r5, #4] mov r1, r8 bic r3, r3, #32 str r3, [r5, #4] mov r2, r7 mov r3, r9 mov r0, r5 bl sdlockctl2 ldr r2, [r5, #68] mov r4, r0 ldr r1, .L736 mov r3, r6 mov r0, r5 str r6, [sp, #0] bl sdcmd2 mov r3, r6 mov r0, r5 ldr r1, .L736+4 mov r2, #2 str r6, [sp, #0] bl sdcmd2 ldr r3, [r5, #4] mov r0, r4 orr r3, r3, #32 str r3, [r5, #4] b .L651 .L654: cmp r8, #8 strb r8, [sp, #32] beq .L714 mov r3, #16 mov r4, r2 strb r3, [sp, #33] add r2, sp, #34 .L660: ldrb r3, [r7, r4] @ zero_extendqisi2 add r4, r4, #1 cmp r4, #15 strb r3, [r2], #1 ble .L660 cmp r8, #8 movne r7, #18 bne .L662 .L714: mov r7, #1 .L662: add sl, sp, #8 mov ip, #0 mov r0, r5 mov r1, #592 mov r2, r7 mov r3, sl str ip, [sp, #0] bl sdcmd2 cmp r0, #0 mov r4, r0 bne .L735 mov r0, sl mov r1, #592 bl error cmp r0, #0 bne .L735 mov r2, r4 mov r0, r5 ldr r1, .L736+8 mov r3, sl str r4, [sp, #0] bl sdcmd2 cmp r0, #0 mov r4, r0 bne .L735 mov r0, sl ldr r1, .L736+8 bl error cmp r0, #0 bne .L735 .L665: cmp r4, r7 bge .L718 ldrb r6, [fp], #1 @ zero_extendqisi2 mov r0, r5 mov r1, r6 bl sd_1bit_feedcrc mov ip, #7 .L673: mov r2, r6, lsr #7 and r2, r2, #1 ldr r3, [r5, #0] orr r1, r2, #30 strb r1, [r3, #0] ldr r3, [r5, #0] orr r1, r2, #62 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 strb r1, [r3, #0] ldr r3, [r5, #0] subs ip, ip, #1 ldrb r3, [r3, #0] @ zero_extendqisi2 mov r6, r6, asl #1 bpl .L673 add r4, r4, #1 b .L665 .L718: mov r4, #0 .L682: mov r0, r5 bl sd_1bit_getcrc mov ip, #7 .L681: mov r2, r0, lsr #7 and r2, r2, #1 ldr r3, [r5, #0] orr r1, r2, #30 strb r1, [r3, #0] ldr r3, [r5, #0] orr r1, r2, #62 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 strb r1, [r3, #0] ldr r2, [r5, #0] subs ip, ip, #1 mov r0, r0, asl #1 ldrb r3, [r2, #0] @ zero_extendqisi2 bpl .L681 add r4, r4, #1 cmp r4, #1 ble .L682 mov r3, #31 strb r3, [r2, #0] ldr r2, [r5, #0] mov r0, #0 ldrb r3, [r2, #0] @ zero_extendqisi2 mvn r3, #64 strb r3, [r2, #0] mov r4, #6 .L686: ldr r2, [r5, #0] mvn r3, #96 strb r3, [r2, #0] ldr r3, [r5, #0] subs r4, r4, #1 ldrb r2, [r3, #0] @ zero_extendqisi2 mvn r2, #64 ldrb r1, [r3, #0] @ zero_extendqisi2 strb r2, [r3, #0] ldr r3, [r5, #0] and r1, r1, #1 orr r0, r1, r0, asl #1 ldrb r3, [r3, #0] @ zero_extendqisi2 bpl .L686 and r3, r0, #15 cmp r3, #5 bne .L735 mov r0, #0 .L694: ldr r2, [r5, #168] ldr r3, .L736+12 add r1, r2, #1 cmp r2, r3 bhi .L689 ldr r2, [r5, #0] mvn r3, #96 str r1, [r5, #168] strb r3, [r2, #0] ldr r3, [r5, #0] mvn r1, #64 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 strb r1, [r3, #0] and r2, r2, #1 orr r0, r2, r0, asl #1 and r3, r0, #7 ldr r2, [r5, #0] cmp r3, #7 ldrb r3, [r2, #0] @ zero_extendqisi2 bne .L694 .L689: mov r4, #7 .L698: ldr r2, [r5, #0] mvn r3, #96 strb r3, [r2, #0] ldr r3, [r5, #0] subs r4, r4, #1 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 mvn r2, #64 strb r2, [r3, #0] ldr r3, [r5, #0] ldrb r3, [r3, #0] @ zero_extendqisi2 bpl .L698 ldr r3, [r5, #4] mov ip, #0 bic r3, r3, #2 str r3, [r5, #4] mov r0, r5 mov r1, #592 mov r2, #512 mov r3, sl str ip, [sp, #0] bl sdcmd2 cmp r0, #0 mov r4, r0 bne .L735 mov r0, sl mov r1, #592 bl error cmp r0, #0 bne .L735 ldr r2, [r5, #68] mov r0, r5 ldr r1, .L736+16 mov r3, sl str r4, [sp, #0] bl sdcmd2 cmp r0, #0 mov r4, r0 bne .L735 mov r0, sl ldr r1, .L736+16 bl error cmp r0, #0 bne .L735 cmp r8, #0 cmpne r8, #8 beq .L704 cmp r8, #2 bne .L703 .L704: ldr r3, [sp, #12] tst r3, #2 beq .L703 .L735: mov r0, #1 b .L651 .L703: cmp r9, #0 beq .L705 mov r3, #0 strb r3, [r9, #0] mov r4, #1 add r6, sp, #33 .L709: ldrb r1, [r6], #1 @ zero_extendqisi2 mov r0, r5 strb r1, [r9, r4] add r4, r4, #1 bl sd_1bit_feedcrc cmp r4, #17 ble .L709 mov r0, r5 bl sd_1bit_getcrc strb r0, [r9, #18] mov r0, r5 bl sd_1bit_getcrc strb r0, [r9, #19] .L705: mov r4, #7 .L713: ldr r2, [r5, #0] mvn r3, #96 strb r3, [r2, #0] ldr r3, [r5, #0] subs r4, r4, #1 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 mvn r2, #64 strb r2, [r3, #0] ldr r3, [r5, #0] ldrb r3, [r3, #0] @ zero_extendqisi2 bpl .L713 mov r0, #0 .L651: add sp, sp, #60 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} bx lr .L737: .align 2 .L736: .word 631 .word 582 .word 1386 .word 1000000 .word 589 .size sdlockctl2, .-sdlockctl2 .section .text.sdlockctl,"ax",%progbits .align 2 .global sdlockctl .type sdlockctl, %function sdlockctl: @ Function supports interworking. @ args = 0, pretend = 0, frame = 56 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, lr} mov r6, r0 ldr ip, [r6, #176] ldr r0, [r0, #96] sub sp, sp, #64 ldr lr, [r6, #92] mov r0, r0, lsr #4 add r9, sp, #40 cmp ip, #0 orr r0, r0, lr, asl #4 str r9, [sp, #12] mov r5, r1 mov r8, r2 mov sl, r3 beq .L739 mov r0, r6 bl sdlockctl2 b .L738 .L739: tst r0, #128 beq .L786 rsbs r3, r2, #1 movcc r3, #0 cmp r1, #8 moveq r3, #0 cmp r3, #0 bne .L786 mov r0, r6 bl stop cmp r0, #0 mov r7, r0 bne .L786 ldr r3, [r6, #4] ands r2, r3, #32 beq .L743 ldr r3, [r6, #0] ldr r2, [r6, #68] ldrb r4, [r3, #3] @ zero_extendqisi2 ldr r1, .L787 mov r3, r0 mov r0, r6 str r7, [sp, #0] bl sdcmd ldr r1, .L787+4 mov r2, r7 mov r3, r7 mov r0, r6 str r7, [sp, #0] bl sdcmd ldr r2, [r6, #0] mov r3, #32 strb r3, [r2, #3] ldr r3, [r6, #4] mov r1, r5 bic r3, r3, #32 str r3, [r6, #4] mov r2, r8 mov r3, sl mov r0, r6 bl sdlockctl ldr r2, [r6, #68] mov r5, r0 ldr r1, .L787 mov r3, r7 mov r0, r6 str r7, [sp, #0] bl sdcmd mov r3, r7 mov r2, #2 mov r0, r6 ldr r1, .L787+4 str r7, [sp, #0] bl sdcmd ldmia r6, {r2, r3} @ phole ldm and r4, r4, #255 orr r3, r3, #32 mov r0, r5 str r3, [r6, #4] strb r4, [r2, #3] b .L738 .L743: cmp r5, #8 strb r5, [sp, #40] beq .L776 mov r3, #16 mov r4, r2 strb r3, [sp, #41] add r2, sp, #42 .L749: ldrb r3, [r8, r4] @ zero_extendqisi2 add r4, r4, #1 cmp r4, #15 strb r3, [r2], #1 ble .L749 cmp r5, #8 movne r8, #18 bne .L751 .L776: mov r8, #1 .L751: add r7, sp, #16 mov ip, #0 mov r0, r6 mov r1, #592 mov r2, r8 mov r3, r7 str ip, [sp, #0] bl sdcmd cmp r0, #0 mov r4, r0 bne .L786 mov r0, r7 mov r1, #592 bl error cmp r0, #0 bne .L786 mov r2, r4 mov r0, r6 ldr r1, .L787+8 mov r3, r7 str r4, [sp, #0] bl sdcmd cmp r0, #0 mov r4, r0 bne .L786 mov r0, r7 ldr r1, .L787+8 bl error cmp r0, #0 bne .L786 .L754: ldr r3, [sp, #12] rsb r3, r9, r3 cmp r3, r8 beq .L780 ldr ip, [r6, #168] ldr r3, .L787+12 mov r0, r6 cmp ip, r3 mov r1, #0 add r2, sp, #12 add lr, ip, #1 bhi .L786 str lr, [r6, #168] bl tend_ssp b .L754 .L780: ldr r3, [r6, #4] ands r1, r3, #32 movne r1, #0 movne r2, #8 moveq r2, #2 movne r0, r6 moveq r0, r6 bl datssp_stream ldr r2, [r6, #0] mvn r3, #121 strb r3, [r2, #2] ldr r3, [r6, #4] mov ip, #0 bic r3, r3, #2 str r3, [r6, #4] mov r0, r6 mov r1, #592 mov r2, #512 mov r3, r7 str ip, [sp, #0] bl sdcmd cmp r0, #0 mov r4, r0 bne .L786 mov r0, r7 mov r1, #592 bl error cmp r0, #0 bne .L786 ldr r2, [r6, #68] mov r0, r6 ldr r1, .L787+16 mov r3, r7 str r4, [sp, #0] bl sdcmd cmp r0, #0 mov r4, r0 bne .L786 mov r0, r7 ldr r1, .L787+16 bl error cmp r0, #0 bne .L786 cmp r5, #0 cmpne r5, #8 beq .L770 cmp r5, #2 bne .L769 .L770: ldr r3, [sp, #20] tst r3, #2 beq .L769 .L786: mov r0, #1 b .L738 .L769: cmp sl, #0 beq .L771 mov r3, #0 strb r3, [sl, #0] mov r4, #1 add r5, sp, #41 .L775: ldrb r1, [r5], #1 @ zero_extendqisi2 mov r0, r6 strb r1, [sl, r4] add r4, r4, #1 bl sd_1bit_feedcrc cmp r4, #17 ble .L775 mov r0, r6 bl sd_1bit_getcrc strb r0, [sl, #18] mov r0, r6 bl sd_1bit_getcrc strb r0, [sl, #19] .L771: mov r0, #0 .L738: add sp, sp, #64 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, lr} bx lr .L788: .align 2 .L787: .word 631 .word 582 .word 1386 .word 1000000 .word 589 .size sdlockctl, .-sdlockctl .section .text.sdreset,"ax",%progbits .align 2 .global sdreset .type sdreset, %function sdreset: @ Function supports interworking. @ args = 0, pretend = 0, frame = 208 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, lr} mov r4, #0 mov r5, r0 sub sp, sp, #220 str r4, [r0, #168] bl sd_initcrc str r4, [r5, #172] str r4, [r5, #36] str r4, [r5, #48] str r4, [r5, #188] mov r0, r5 bl version cmp r0, #1 str r0, [r5, #176] bls .L791 str r4, [r5, #168] mov r0, r5 bl sd_initcrc ldr r3, [r5, #176] str r4, [r5, #172] cmp r3, r4 str r4, [r5, #36] str r4, [r5, #48] str r4, [r5, #188] bne .L794 mov r0, r5 bl version cmp r0, r4 str r0, [r5, #176] bne .L794 b .L954 .L938: str r5, [r4, r0, asl #2] b .L797 .L794: ldr r3, [r5, #4] mov r0, r4 and r3, r3, #1024 str r3, [r5, #4] mov ip, r4 .L804: ldr r4, .L955 ldr r1, [r4, r0, asl #2] cmp r1, #0 bne .L799 cmp ip, #0 movne r3, #1024 str r5, [r4, r0, asl #2] strne r3, [r5, #4] b .L797 .L799: ldr r2, [r1, #0] ldr r3, [r5, #0] cmp r2, r3 bne .L798 ldr r2, [r1, #64] ldr r3, [r5, #64] mov ip, #1 cmp r2, r3 beq .L938 .L798: add r0, r0, #1 cmp r0, #255 bls .L804 .L797: mov r0, r5 bl activate ldr r3, [r5, #4] orr r3, r3, #256 ands r1, r3, #1024 str r3, [r5, #4] bne .L806 ldr r2, [r5, #0] ldrb r3, [r2, #0] @ zero_extendqisi2 cmp r3, #0 beq .L806 strb r1, [r2, #0] ldr r3, [r5, #0] mov lr, r1 .L810: strh lr, [r3, #2] @ movhi add lr, lr, #1 cmp lr, #7 bls .L810 ldr r0, [r5, #12] ldr r1, .L955+4 ldr ip, [r5, #24] mov lr, pc bx ip mov lr, #0 .L816: ldr r1, [r4, lr, asl #2] add lr, lr, #1 cmp r1, #0 beq .L812 ldr r3, [r5, #0] ldr r2, [r1, #0] cmp r2, r3 ldreq r3, [r1, #4] orreq r3, r3, #1024 streq r3, [r1, #4] cmp lr, #255 bls .L816 .L812: ldr r2, [r5, #0] ldr r3, [r5, #64] strh r3, [r2, #2] @ movhi .L806: ldmia r5, {r2, r3} @ phole ldm bic r3, r3, #1024 str r3, [r5, #4] mvn r3, #0 strb r3, [r2, #0] ldr r1, .L955+8 ldr r0, [r5, #12] ldr ip, [r5, #24] mov lr, pc bx ip ldr r1, .L955+12 mov lr, #0 .L820: ldr r2, [r5, #0] mvn r3, #0 strb r3, [r2, #0] ldr r3, [r5, #0] add lr, lr, #1 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 mvn r2, #32 strb r2, [r3, #0] ldr r2, [r5, #0] cmp lr, r1 ldrb r3, [r2, #0] @ zero_extendqisi2 ldrb r3, [r2, #0] @ zero_extendqisi2 bls .L820 ldrb r3, [r2, #1] @ zero_extendqisi2 add r7, sp, #72 mov r3, #24 strb r3, [r2, #1] mov r4, #0 mov r0, r5 mov r1, #584 ldr r2, .L955+16 mov r3, r7 str r4, [sp, #0] bl sdcmd2 cmp r0, r4 ldreq r6, .L955+20 movne r6, #16711680 strne r4, [r5, #168] .L824: mov r4, #0 ldr r1, .L955+24 mov r2, r4 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd2 ldr r1, .L955+28 mov r2, r6 mov r3, r7 mov r0, r5 str r4, [sp, #0] bl sdcmd2 ldr r2, [r5, #168] ldr r3, .L955+32 add r1, r2, #1 cmp r2, r3 bhi .L825 ldr r3, [sp, #76] str r1, [r5, #168] tst r3, #128 beq .L824 .L825: tst r6, #1073741824 beq .L831 ldr r3, [sp, #76] tst r3, #64 ldrne r3, [r5, #4] orrne r3, r3, #64 strne r3, [r5, #4] .L831: mov r4, #0 ldr r1, .L955+36 mov r2, r4 mov r3, r7 mov r0, r5 str r4, [sp, #0] bl sdcmd2 ldr r1, .L955+40 mov r2, r4 mov r3, r7 mov r0, r5 str r4, [sp, #0] bl sdcmd2 ldr r3, [sp, #76] ldr r2, [sp, #80] ldr r1, .L955+44 orr r2, r2, r3, asl #8 and r3, r2, #255 mov r3, r3, asl #16 and r2, r2, #65280 orr r3, r3, r2, asl #16 mvn r2, r3 str r2, [r5, #40] str r3, [r5, #68] mov r2, r3 mov r0, r5 add r3, r5, #72 str r4, [sp, #0] bl sdcmd2 ldr r2, [r5, #68] mov r3, r7 mov r0, r5 ldr r1, .L955+48 str r4, [sp, #0] bl sdcmd2 ldr r3, [sp, #76] ands r3, r3, #2 streq r3, [r5, #56] beq .L835 ldr r2, [r5, #52] mov r0, #1 cmp r2, r4 str r0, [r5, #56] beq .L917 mov r1, r4 mov r0, r5 mov r3, r4 bl sdlockctl2 cmp r0, r4 bne .L917 .L835: mov r4, #0 ldr r2, [r5, #68] ldr r1, .L955+24 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd2 ldr r1, .L955+52 mov r2, r4 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd2 mov r1, #592 mov r2, #512 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd2 ldr r2, [r5, #68] ldr r1, .L955+24 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd2 mov r3, r7 ldr r1, .L955+56 mov r2, #2 mov r0, r5 str r4, [sp, #0] bl sdcmd2 ldr r3, [r5, #4] ldr r2, [r5, #68] orr r3, r3, #32 bic r3, r3, #256 str r3, [r5, #4] ldr r1, .L955+24 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd2 mov r2, r4 mov r0, r5 ldr r1, .L955+60 mov r3, r4 str r4, [sp, #0] bl sdcmd2 .L836: ldr r2, [r5, #168] ldr r3, .L955+32 add r1, r2, #1 cmp r2, r3 bhi .L837 ldr r2, [r5, #0] mvn r3, #32 str r1, [r5, #168] strb r3, [r2, #0] ldr r3, [r5, #0] ldrb r2, [r3, #0] @ zero_extendqisi2 mvn r2, #0 ldrb r1, [r3, #0] @ zero_extendqisi2 strb r2, [r3, #0] ldr r3, [r5, #0] tst r1, #15 ldrb r3, [r3, #0] @ zero_extendqisi2 bne .L836 .L837: mov lr, #0 add r4, r5, #176 .L847: ldr r3, [r5, #0] mvn r2, #32 strb r2, [r3, #0] ldr r3, [r5, #0] mvn r0, #0 ldrb r1, [r3, #0] @ zero_extendqisi2 ldrb r1, [r3, #0] @ zero_extendqisi2 strb r0, [r3, #0] ldr r3, [r5, #0] and r1, r1, #15 ldrb ip, [r3, #0] @ zero_extendqisi2 strb r2, [r3, #0] ldr r3, [r5, #0] cmp lr, #7 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 strb r0, [r3, #0] ldr r3, [r5, #0] and r2, r2, #15 add lr, lr, #1 orr r0, r2, r1, asl #4 ldrb r3, [r3, #0] @ zero_extendqisi2 strlsb r0, [r4, #4] cmp lr, #15 add r4, r4, #1 bls .L847 mov lr, #7 .L851: ldr r2, [r5, #0] mvn r3, #32 strb r3, [r2, #0] ldr r3, [r5, #0] ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 mvn r2, #0 strb r2, [r3, #0] ldr r3, [r5, #0] adds lr, lr, r2 ldrb r3, [r3, #0] @ zero_extendqisi2 bpl .L851 ldr r3, [r5, #4] ldrb r2, [r5, #180] @ zero_extendqisi2 bic r3, r3, #1 tst r2, #15 str r3, [r5, #4] beq .L852 mov ip, #0 mov r3, ip mov r0, r5 ldr r1, .L955+64 ldr r2, .L955+68 str ip, [sp, #0] bl sdcmd2 .L853: ldr r2, [r5, #168] ldr r3, .L955+32 add r1, r2, #1 cmp r2, r3 bhi .L854 ldr r2, [r5, #0] mvn r3, #32 str r1, [r5, #168] strb r3, [r2, #0] ldr r3, [r5, #0] ldrb r2, [r3, #0] @ zero_extendqisi2 mvn r2, #0 ldrb r1, [r3, #0] @ zero_extendqisi2 strb r2, [r3, #0] ldr r3, [r5, #0] tst r1, #15 ldrb r3, [r3, #0] @ zero_extendqisi2 bne .L853 .L854: mov lr, #0 add r4, sp, #8 .L864: ldr r3, [r5, #0] mvn r2, #32 strb r2, [r3, #0] ldr r3, [r5, #0] mvn r0, #0 ldrb r1, [r3, #0] @ zero_extendqisi2 ldrb r1, [r3, #0] @ zero_extendqisi2 strb r0, [r3, #0] ldr r3, [r5, #0] and r1, r1, #15 ldrb ip, [r3, #0] @ zero_extendqisi2 strb r2, [r3, #0] ldr r3, [r5, #0] cmp lr, #63 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 strb r0, [r3, #0] ldr r3, [r5, #0] and r2, r2, #15 add lr, lr, #1 orr r0, r2, r1, asl #4 ldrb r3, [r3, #0] @ zero_extendqisi2 strlsb r0, [r4, #0] cmp lr, #71 add r4, r4, #1 bls .L864 mov lr, #7 .L868: ldr r2, [r5, #0] mvn r3, #32 strb r3, [r2, #0] ldr r3, [r5, #0] ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 mvn r2, #0 strb r2, [r3, #0] ldr r0, [r5, #0] adds lr, lr, r2 ldrb r3, [r0, #0] @ zero_extendqisi2 bpl .L868 ldr r3, [r5, #4] ldrb r1, [sp, #8] @ zero_extendqisi2 ldrb r2, [sp, #9] @ zero_extendqisi2 bic r3, r3, #1 orrs r1, r1, r2 str r3, [r5, #4] movne r3, #56 strneb r3, [r0, #1] ldrne r3, [r5, #4] orrne r3, r3, #128 strne r3, [r5, #4] .L852: ldr r3, [r5, #132] tst r3, #48 bne .L871 ldr r3, [r5, #0] ldrh r3, [r3, #0] tst r3, #512 beq .L870 .L871: mov r3, #1 str r3, [r5, #36] .L870: ldr r3, [r5, #96] mov r2, #1 and r3, r3, #15 mov r2, r2, asl r3 ldr r1, [r5, #168] ldr r3, .L955+32 str r2, [r5, #48] cmp r1, r3 addls r3, r1, #1 strls r3, [r5, #168] bls .L916 b .L917 .L791: ldr r2, [r5, #0] ldrb r3, [r2, #3] @ zero_extendqisi2 ands r6, r3, #8 bne .L954 ldr r3, [r5, #40] cmp r3, #0 beq .L878 mov r3, #64 strb r3, [r2, #3] ldr r2, [r5, #40] sub r3, r3, #32 mvn r1, r2 str r3, [r5, #4] str r1, [r5, #68] mov r3, r6 ldr r1, .L955+72 mov r0, r5 str r6, [sp, #0] bl sdcmd ldr r2, [r5, #68] ldr r1, .L955+44 add r3, r5, #72 mov r0, r5 str r6, [sp, #0] bl sdcmd ldr r2, [r5, #68] mov r3, r6 mov r0, r5 ldr r1, .L955+48 str r6, [sp, #0] bl sdcmd ldr r3, [r5, #16] cmp r3, #0 ldrne r2, [r5, #0] movne r3, #66 strneb r3, [r2, #3] ldr r3, [r5, #0] ldrb r3, [r3, #3] @ zero_extendqisi2 tst r3, #128 bne .L881 ldr r3, [r5, #132] tst r3, #48 beq .L880 .L881: mov r3, #1 str r3, [r5, #36] .L880: ldr r3, [r5, #96] mov r2, #1 and r3, r3, #15 mov r2, r2, asl r3 ldr r1, [r5, #168] ldr r3, .L955+32 str r2, [r5, #48] cmp r1, r3 movhi r0, #0 addls r3, r1, #1 strls r3, [r5, #168] movls r0, r5 blls sdsize .L886: mov r3, #0 cmp r0, #0 str r3, [r5, #40] bne .L789 .L878: ldr r2, [r5, #0] mov r3, #32 strb r3, [r2, #3] ldr r2, [r5, #0] sub r3, r3, #32 strb r3, [r2, #2] ldr r2, [r5, #0] add r3, r3, #5 str r3, [r5, #4] ldrb r3, [r2, #2] @ zero_extendqisi2 and r3, r3, #7 .L952: cmp r3, #1 beq .L937 ldr r2, [r5, #168] ldr r3, .L955+32 ldr r1, .L955+76 cmp r2, r3 add ip, r2, #1 bhi .L917 ldr r0, [r5, #12] str ip, [r5, #168] ldr ip, [r5, #24] mov lr, pc bx ip ldr r3, [r5, #168] mov r1, #0 add r3, r3, #9984 add r3, r3, #16 str r3, [r5, #168] mov r0, r5 mov r2, r1 bl tend_ssp and r3, r0, #7 b .L952 .L937: ldr r2, [r5, #0] mov r3, #7 strb r3, [r2, #2] mov r4, #0 ldr r0, [r5, #12] ldr r1, .L955+80 str r4, [r5, #4] ldr ip, [r5, #24] mov lr, pc bx ip ldr r3, [r5, #0] ldr r1, .L955+4 strb r4, [r3, #2] ldr r0, [r5, #12] ldr ip, [r5, #24] mov lr, pc bx ip ldr r2, [r5, #0] ldrb r3, [r2, #2] @ zero_extendqisi2 and r3, r3, #7 cmp r3, #7 bne .L896 .L954: mov r0, r4 b .L789 .L896: mov r3, #2 strb r3, [r2, #2] ldr r0, [r5, #12] ldr r1, .L955+80 ldr ip, [r5, #24] mov lr, pc bx ip ldr r3, [r5, #0] add r7, sp, #144 strb r4, [r3, #2] mov r0, r5 mov r3, r7 mov r1, #584 ldr r2, .L955+16 str r4, [sp, #0] bl sdcmd cmp r0, #0 ldrne r3, [r5, #0] ldreq r6, .L955+20 strne r4, [r5, #168] movne r6, #16711680 strneb r4, [r3, #2] .L900: mov r4, #0 ldr r1, .L955+24 mov r2, r4 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd ldr r1, .L955+28 mov r2, r6 mov r3, r7 mov r0, r5 str r4, [sp, #0] bl sdcmd ldr r2, [r5, #168] ldr r3, .L955+32 add r1, r2, #1 cmp r2, r3 bhi .L901 ldr r3, [sp, #148] str r1, [r5, #168] tst r3, #128 beq .L900 .L901: tst r6, #1073741824 beq .L907 ldr r3, [sp, #148] tst r3, #64 ldrne r3, [r5, #4] orrne r3, r3, #64 strne r3, [r5, #4] .L907: mov r4, #0 ldr r1, .L955+36 mov r2, r4 mov r3, r7 mov r0, r5 str r4, [sp, #0] bl sdcmd ldr r1, .L955+40 mov r2, r4 mov r3, r7 mov r0, r5 str r4, [sp, #0] bl sdcmd ldr r3, [sp, #148] ldr r2, [sp, #152] ldr r1, .L955+44 orr r2, r2, r3, asl #8 and r3, r2, #255 mov r3, r3, asl #16 and r2, r2, #65280 orr r3, r3, r2, asl #16 mvn r2, r3 str r2, [r5, #40] str r3, [r5, #68] mov r2, r3 mov r0, r5 add r3, r5, #72 str r4, [sp, #0] bl sdcmd ldr r2, [r5, #68] mov r3, r7 mov r0, r5 ldr r1, .L955+48 str r4, [sp, #0] bl sdcmd ldr r3, [sp, #148] ands r3, r3, #2 streq r3, [r5, #56] beq .L911 ldr r2, [r5, #52] mov r0, #1 cmp r2, r4 str r0, [r5, #56] beq .L917 mov r1, r4 mov r0, r5 mov r3, r4 bl sdlockctl cmp r0, r4 bne .L917 .L911: mov r4, #0 ldr r2, [r5, #68] ldr r1, .L955+24 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd ldr r1, .L955+52 mov r2, r4 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd mov r1, #592 mov r2, #512 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd ldr r2, [r5, #68] ldr r1, .L955+24 mov r3, r4 mov r0, r5 str r4, [sp, #0] bl sdcmd mov r2, #2 mov r3, r7 mov r0, r5 ldr r1, .L955+56 str r4, [sp, #0] bl sdcmd ldr r3, [r5, #16] ldr r2, [r5, #0] cmp r3, r4 movne r3, #66 moveq r3, #64 strb r3, [r2, #3] ldmia r5, {r2, r3} @ phole ldm orr r3, r3, #32 str r3, [r5, #4] ldrb r3, [r2, #3] @ zero_extendqisi2 tst r3, #128 bne .L915 ldr r3, [r5, #132] tst r3, #48 beq .L914 .L915: mov r3, #1 str r3, [r5, #36] .L914: ldr r3, [r5, #96] mov r2, #1 and r3, r3, #15 mov r2, r2, asl r3 ldr r1, [r5, #168] ldr r3, .L955+32 str r2, [r5, #48] cmp r1, r3 bhi .L917 add r3, r1, #1 str r3, [r5, #168] mov r0, r7 ldr r1, .L955+56 bl error cmp r0, #0 beq .L916 .L917: mov r0, #0 b .L789 .L916: mov r0, r5 bl sdsize .L789: add sp, sp, #220 ldmfd sp!, {r4, r5, r6, r7, lr} bx lr .L956: .align 2 .L955: .word sdcores .word 100000 .word 5000 .word 749 .word 426 .word 1090453504 .word 631 .word 617 .word 1000000 .word 834 .word 579 .word 841 .word 1095 .word 618 .word 582 .word 1907 .word 1862 .word -2130706447 .word 327 .word 10000 .word 50000 .size sdreset, .-sdreset .section .text.sdread,"ax",%progbits .align 2 .global sdread .type sdread, %function sdread: @ Function supports interworking. @ args = 0, pretend = 0, frame = 8 @ frame_needed = 0, uses_anonymous_args = 0 str lr, [sp, #-4]! mov lr, r0 ldr ip, [lr, #176] sub sp, sp, #12 cmp ip, #0 stmia sp, {r2, r3} @ phole stm mov r2, sp mov r3, #1 bne .L958 bl do_read b .L959 .L958: mov r0, lr mov r2, sp mov r3, #1 bl do_read2 .L959: add sp, sp, #12 ldr lr, [sp], #4 bx lr .size sdread, .-sdread .section .text.sdwrite,"ax",%progbits .align 2 .global sdwrite .type sdwrite, %function sdwrite: @ Function supports interworking. @ args = 0, pretend = 0, frame = 8 @ frame_needed = 0, uses_anonymous_args = 0 str lr, [sp, #-4]! mov lr, r0 ldr ip, [lr, #176] sub sp, sp, #12 cmp ip, #0 stmia sp, {r2, r3} @ phole stm mov r2, sp mov r3, #1 bne .L961 bl do_write b .L962 .L961: mov r0, lr mov r2, sp mov r3, #1 bl do_write2 .L962: add sp, sp, #12 ldr lr, [sp], #4 bx lr .size sdwrite, .-sdwrite .section .text.sdreadv,"ax",%progbits .align 2 .global sdreadv .type sdreadv, %function sdreadv: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 @ link register save eliminated. mov ip, r0 ldr r0, [r0, #176] @ lr needed for prologue cmp r0, #0 bne .L964 mov r0, ip b do_read .L964: mov r0, ip b do_read2 .size sdreadv, .-sdreadv .section .text.sdwritev,"ax",%progbits .align 2 .global sdwritev .type sdwritev, %function sdwritev: @ Function supports interworking. @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 @ link register save eliminated. mov ip, r0 ldr r0, [r0, #176] @ lr needed for prologue cmp r0, #0 bne .L967 mov r0, ip b do_write .L967: mov r0, ip b do_write2 .size sdwritev, .-sdwritev .section .text.sdsetwprot,"ax",%progbits .align 2 .global sdsetwprot .type sdsetwprot, %function sdsetwprot: @ Function supports interworking. @ args = 0, pretend = 0, frame = 216 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, lr} ldr r3, [r0, #176] sub sp, sp, #224 cmp r3, #0 add r3, sp, #120 mov r5, r0 str r3, [sp, #12] mov r4, r1 beq .L970 bl stop2 cmp r4, #0 moveq r1, #1 movne r1, #3 add r8, sp, #16 mov r6, #0 .L976: mov r3, r6, asl #2 add r2, r3, r5 ldr r2, [r2, #76] add r6, r6, #1 add r0, sp, #224 add r3, r3, r0 cmp r6, #15 str r2, [r3, #-168] ble .L976 ldr r3, [sp, #112] mov r0, #0 bic r3, r3, #48 orr r3, r3, r1, asl #4 str r3, [sp, #112] add r4, sp, #56 mov lr, r0 .L985: ldrb r1, [r4, #0] @ zero_extendqisi2 mov ip, #0 .L984: add r3, ip, #1 mov r0, r0, asl #1 and ip, r3, #255 eor r3, r1, r0 tst r3, #128 mov r2, r1, asl #1 eorne r0, r0, #9 cmp ip, #7 and r1, r2, #255 bls .L984 add lr, lr, #1 cmp lr, #15 and r0, r0, #127 add r4, r4, #4 bcc .L985 mov r3, r0, asl #1 orr r3, r3, #1 str r3, [sp, #116] add r1, sp, #16 add r2, sp, #224 mov r6, #15 .L990: ldr r3, [r2, #-168] subs r6, r6, #1 strb r3, [r1], #1 add r2, r2, #4 bpl .L990 mov ip, #0 add r7, sp, #32 mov r2, ip mov r0, r5 ldr r1, .L1071 mov r3, r7 str ip, [sp, #0] bl sdcmd2 cmp r0, #0 mov r4, r0 bne .L1044 mov r0, r7 ldr r1, .L1071 bl error cmp r0, #0 bne .L1044 mov r6, #15 .L997: ldrb r4, [r8], #1 @ zero_extendqisi2 mov r0, r5 mov r1, r4 bl sd_4bit_feedcrc ldr r1, [r5, #0] mov r2, r4, lsr #4 orr r3, r2, #16 strb r3, [r1, #0] ldr r3, [r5, #0] orr r2, r2, #48 ldrb r1, [r3, #0] @ zero_extendqisi2 ldrb r1, [r3, #0] @ zero_extendqisi2 strb r2, [r3, #0] ldr r3, [r5, #0] and r4, r4, #15 orr r2, r4, #16 ldrb r1, [r3, #0] @ zero_extendqisi2 strb r2, [r3, #0] ldr r3, [r5, #0] orr r4, r4, #48 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 strb r4, [r3, #0] ldr r3, [r5, #0] subs r6, r6, #1 ldrb r3, [r3, #0] @ zero_extendqisi2 bpl .L997 mov r6, #7 .L1001: mov r0, r5 bl sd_4bit_getcrc and r2, r0, #240 ldr r1, [r5, #0] mov r2, r2, asr #4 orr r3, r2, #16 strb r3, [r1, #0] ldr r3, [r5, #0] orr r2, r2, #48 ldrb r1, [r3, #0] @ zero_extendqisi2 ldrb r1, [r3, #0] @ zero_extendqisi2 strb r2, [r3, #0] ldr r3, [r5, #0] and r2, r0, #15 orr r1, r2, #16 ldrb r0, [r3, #0] @ zero_extendqisi2 strb r1, [r3, #0] ldr r3, [r5, #0] orr r2, r2, #48 ldrb r1, [r3, #0] @ zero_extendqisi2 ldrb r1, [r3, #0] @ zero_extendqisi2 strb r2, [r3, #0] ldr r2, [r5, #0] subs r6, r6, #1 ldrb r3, [r2, #0] @ zero_extendqisi2 bpl .L1001 mov r3, #31 strb r3, [r2, #0] ldr r3, [r5, #0] mov r0, #0 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 mov r2, #63 strb r2, [r3, #0] ldr r2, [r5, #0] mov r6, #6 ldrb r3, [r2, #0] @ zero_extendqisi2 mvn r3, #64 strb r3, [r2, #0] .L1005: ldr r2, [r5, #0] mvn r3, #96 strb r3, [r2, #0] ldr r1, [r5, #0] mvn r2, #64 ldrb r3, [r1, #0] @ zero_extendqisi2 ldrb r3, [r1, #0] @ zero_extendqisi2 subs r6, r6, #1 and r3, r3, #1 strb r2, [r1, #0] orr r0, r3, r0, asl #1 bpl .L1005 and r3, r0, #15 cmp r3, #5 bne .L1044 mov r0, #0 .L1013: ldr r2, [r5, #168] ldr r3, .L1071+4 add r1, r2, #1 cmp r2, r3 bhi .L1008 ldr r2, [r5, #0] mvn r3, #96 str r1, [r5, #168] strb r3, [r2, #0] ldr r3, [r5, #0] mvn r1, #64 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 strb r1, [r3, #0] and r2, r2, #1 orr r0, r2, r0, asl #1 and r3, r0, #7 cmp r3, #7 bne .L1013 .L1008: mov r6, #7 .L1017: ldr r2, [r5, #0] mvn r3, #96 strb r3, [r2, #0] ldr r3, [r5, #0] subs r6, r6, #1 ldrb r2, [r3, #0] @ zero_extendqisi2 ldrb r2, [r3, #0] @ zero_extendqisi2 mvn r2, #64 strb r2, [r3, #0] ldr r3, [r5, #0] ldrb r3, [r3, #0] @ zero_extendqisi2 bpl .L1017 ldr r3, [r5, #4] ldr r2, [r5, #68] mov r4, #0 bic r3, r3, #2 str r3, [r5, #4] mvn r2, r2 mov r3, r4 ldr r1, .L1071+8 mov r0, r5 str r4, [sp, #0] bl sdcmd2 ldr r2, [r5, #68] mov r0, r5 ldr r1, .L1071+12 add r3, r5, #72 str r4, [sp, #0] bl sdcmd2 cmp r0, #0 mov r4, r0 bne .L1044 ldr r2, [r5, #132] ldr r3, [sp, #112] cmp r2, r3 bne .L1044 ldr r2, [r5, #68] mov r3, r7 mov r0, r5 ldr r1, .L1071+16 str r4, [sp, #0] bl sdcmd2 mov r3, #1 mov r0, r4 str r3, [r5, #36] b .L969 .L970: bl stop cmp r0, #0 bne .L1044 cmp r4, #0 moveq r1, #1 movne r1, #3 mov r4, r0 .L1026: mov r3, r4, asl #2 add r2, r3, r5 ldr r2, [r2, #76] add r4, r4, #1 add r0, sp, #224 add r3, r3, r0 cmp r4, #15 str r2, [r3, #-64] ble .L1026 ldr r3, [sp, #216] mov r0, #0 bic r3, r3, #48 orr r3, r3, r1, asl #4 str r3, [sp, #216] add r4, sp, #160 mov lr, r0 .L1035: ldrb r1, [r4, #0] @ zero_extendqisi2 mov ip, #0 .L1034: add r3, ip, #1 mov r0, r0, asl #1 and ip, r3, #255 eor r3, r1, r0 tst r3, #128 mov r2, r1, asl #1 eorne r0, r0, #9 cmp ip, #7 and r1, r2, #255 bls .L1034 add lr, lr, #1 cmp lr, #15 and r0, r0, #127 add r4, r4, #4 bcc .L1035 mov r3, r0, asl #1 orr r3, r3, #1 str r3, [sp, #220] add r1, sp, #120 add r2, sp, #224 mov r4, #15 .L1040: ldr r3, [r2, #-64] subs r4, r4, #1 strb r3, [r1], #1 add r2, r2, #4 bpl .L1040 mov ip, #0 add r7, sp, #136 mov r2, ip mov r0, r5 ldr r1, .L1071 mov r3, r7 str ip, [sp, #0] bl sdcmd cmp r0, #0 mov r6, r0 mov r4, #16 bne .L1044 mov r0, r7 ldr r1, .L1071 bl error cmp r0, #0 bne .L1044 mov r2, r4 add r1, sp, #12 mov r0, r5 bl datssp_stream mov r1, r6 mov r2, #8 mov r0, r5 bl datssp_stream ldr r2, [r5, #0] mvn r3, #121 strb r3, [r2, #2] ldr r3, [r5, #4] ldr r2, [r5, #68] bic r3, r3, #2 str r3, [r5, #4] mvn r2, r2 mov r3, r6 ldr r1, .L1071+8 mov r0, r5 str r6, [sp, #0] bl sdcmd ldr r2, [r5, #68] mov r0, r5 ldr r1, .L1071+12 add r3, r5, #72 str r6, [sp, #0] bl sdcmd cmp r0, #0 mov r6, r0 bne .L1044 ldr r2, [r5, #132] ldr r3, [sp, #216] cmp r2, r3 beq .L1043 .L1044: mov r0, #1 b .L969 .L1043: ldr r2, [r5, #68] mov r3, r7 mov r0, r5 ldr r1, .L1071+16 str r6, [sp, #0] bl sdcmd mov r3, #1 str r3, [r5, #36] mov r0, r6 .L969: add sp, sp, #224 ldmfd sp!, {r4, r5, r6, r7, r8, lr} bx lr .L1072: .align 2 .L1071: .word 1371 .word 1000000 .word 327 .word 841 .word 1095 .size sdsetwprot, .-sdsetwprot .section .bss.sdcores,"aw",%nobits .align 2 .type sdcores, %object .size sdcores, 256 sdcores: .space 256 .ident "GCC: (GNU) 3.4.4 (release) (CodeSourcery ARM 2005q3-2)"