#include <stdio.h>
#include <string.h>
#include <sys/mman.h>
#include "ts.h"
#include "peekpoke.h"

TS_CPU ts_cpu(void) {
  FILE *cpuinfo;
  char buf[4096];
  static unsigned int checked = 0;
  static TS_CPU cpu = 0;

  if (!checked) {
    cpuinfo = fopen("/proc/cpuinfo", "r");
    if (cpuinfo == NULL) {
      return 0;
    }
    bzero(buf, 4096);
    fread(buf, 1, 4095, cpuinfo);
    fclose(cpuinfo);
    if (strstr(buf, "FA526")) {
      cpu = CPU_CAVIUM;
    } else if (strstr(buf, "ARM920T") && strstr(buf, "crunch")) {
      cpu = CPU_EP9302;
    } else if (strstr(buf,"ARM926EJ-S") && strstr(buf,"Atmel")) {
      cpu = CPU_ATMEL;
    } else if (strstr(buf,"Intel")) {
      cpu = CPU_X86;
    } else {
      cpu = CPU_UNKNOWN;
    }
    checked = 1;
  }
  return cpu;
}

#ifndef OMIT_BOARDID
// returns 0 if it doesn't know what board this is
int ts_boardid(void) {
  TS_CPU cpu = ts_cpu();
  volatile unsigned short *syscon;
  int devmem = -1;
  int id;

  switch (cpu) {
  case CPU_UNKNOWN:
    return 0;
#ifndef CLIENT_ONLY
  case CPU_EP9302:
    // no support for detecting EP9302 boards at the moment...
    return 0;
  case CPU_CAVIUM:
    init_cavium();
    id = cavium_detect_model();
    break;
  case CPU_ATMEL:
    syscon = map_phys(0x30000000,&devmem);
    id = syscon[0];
    munmap((void *)syscon,getpagesize());
    break;
#endif
  case CPU_X86:
    // no support for detecting X86 boards at the moment...
    return 0;
  }
  return id;
}
#endif
/* ATMEL
Processor       : ARM926EJ-S rev 5 (v5l)
BogoMIPS        : 199.47
Features        : swp half thumb fastmult edsp java
CPU implementer : 0x41
CPU architecture: 5TEJ
CPU variant     : 0x0
CPU part        : 0x926
CPU revision    : 5

Hardware        : Atmel AT91SAM9G20-EK
Revision        : 0000
Serial          : 0000000000000000
*/
/* EP9302
Processor       : ARM920T rev 0 (v4l)
BogoMIPS        : 99.73
Features        : swp half thumb crunch
CPU implementer : 0x41
CPU architecture: 4T
CPU variant     : 0x1
CPU part        : 0x920
CPU revision    : 0
Cache type      : write-back
Cache clean     : cp15 c7 ops
Cache lockdown  : format A
Cache format    : Harvard
I size          : 16384
I assoc         : 64
I line length   : 32
I sets          : 8
D size          : 16384
D assoc         : 64
D line length   : 32
D sets          : 8

Hardware        : Technologic Systems TS-72xx SBC
Revision        : 0000
Serial          : 0000000000000000
*/
/* Cavium
Processor       : FA526id(wb) rev 1 (v4l)
BogoMIPS        : 191.69
Features        : swp half
CPU implementer : 0x66
CPU architecture: 4
CPU variant     : 0x0
CPU part        : 0x526
CPU revision    : 1
Cache type      : write-back
Cache clean     : cp15 c7 ops
Cache lockdown  : format B
Cache format    : Harvard
I size          : 8192
I assoc         : 2
I line length   : 16
I sets          : 256
D size          : 8192
D assoc         : 2
D line length   : 16
D sets          : 256

Hardware        : STAR STR8100
Revision        : 0000
Serial          : 0000000000000000
*/